From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Andy Lutomirski <luto@kernel.org>,
"H . Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>
Cc: Andi Kleen <ak@linux.intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Markus T Metzger <markus.t.metzger@intel.com>,
"Ravi V . Shankar" <ravi.v.shankar@intel.com>,
"Chang S . Bae" <chang.seok.bae@intel.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 7/8] x86/segments/32: Introduce CPU_NUMBER segment
Date: Wed, 6 Jun 2018 09:23:18 -0700 [thread overview]
Message-ID: <1528302199-29619-8-git-send-email-chang.seok.bae@intel.com> (raw)
In-Reply-To: <1528302199-29619-1-git-send-email-chang.seok.bae@intel.com>
The new entry will be equivalent to that of x86-64 which
stores CPU number. The entry is placed in segment 23 in GDT
by bumping down 23-28 by one, which are all kernel-internal
segments and so have no impact on user space.
CPU_NUMBER segment will always be at '%ss (USER_DS) + 80'
for the default (flat, initial) user space %ss. %ss is
specified than %ds because it is less likely to be changed
as 64-bit has %ss defined.
Suggested-by: H. Peter <hpa@zytor.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/segment.h | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h
index 492e3d1..fca55d7 100644
--- a/arch/x86/include/asm/segment.h
+++ b/arch/x86/include/asm/segment.h
@@ -77,14 +77,14 @@
* 20 - PNPBIOS support <=== cacheline #6
* 21 - PNPBIOS support
* 22 - PNPBIOS support
- * 23 - APM BIOS support
+ * 23 - CPU number
* 24 - APM BIOS support <=== cacheline #7
* 25 - APM BIOS support
*
- * 26 - ESPFIX small SS
- * 27 - per-cpu [ offset to per-cpu data area ]
- * 28 - stack_canary-20 [ for stack protector ] <=== cacheline #8
- * 29 - unused
+ * 26 - APM BIOS support
+ * 27 - ESPFIX small SS
+ * 28 - per-cpu [ offset to per-cpu data area ] <=== cacheline #8
+ * 29 - stack_canary-20 [ for stack protector ]
* 30 - unused
* 31 - TSS for double fault handler
*/
@@ -102,11 +102,12 @@
#define GDT_ENTRY_PNPBIOS_DS 20
#define GDT_ENTRY_PNPBIOS_TS1 21
#define GDT_ENTRY_PNPBIOS_TS2 22
-#define GDT_ENTRY_APMBIOS_BASE 23
+#define GDT_ENTRY_CPU_NUMBER 23
+#define GDT_ENTRY_APMBIOS_BASE 24
-#define GDT_ENTRY_ESPFIX_SS 26
-#define GDT_ENTRY_PERCPU 27
-#define GDT_ENTRY_STACK_CANARY 28
+#define GDT_ENTRY_ESPFIX_SS 27
+#define GDT_ENTRY_PERCPU 28
+#define GDT_ENTRY_STACK_CANARY 29
#define GDT_ENTRY_DOUBLEFAULT_TSS 31
@@ -140,6 +141,13 @@
/* another data segment: */
#define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2*8)
+/*
+ * CPU_NUMBER segment is at '%ss + 80' for the default (flat, initial)
+ * user space %ss (for 64-bit as well). Using %ss than %ds for less
+ * likely to be changed as defined in 64-bit too.
+ */
+#define __CPU_NUMBER_SEG (GDT_ENTRY_CPU_NUMBER*8 + 3)
+
#ifdef CONFIG_SMP
# define __KERNEL_PERCPU (GDT_ENTRY_PERCPU*8)
#else
@@ -206,6 +214,10 @@
#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS*8 + 3)
#define __USER32_DS __USER_DS
#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS*8 + 3)
+/*
+ * CPU_NUMBER segment at '%ss (USER_DS) + 80',
+ * like 32-bit for the same reason
+ */
#define __CPU_NUMBER_SEG (GDT_ENTRY_CPU_NUMBER*8 + 3)
#endif
--
2.7.4
next prev parent reply other threads:[~2018-06-06 16:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-06 16:23 [PATCH v2 0/8] x86: infrastructure to enable FSGSBASE Chang S. Bae
2018-06-06 16:23 ` [PATCH v2 1/8] x86/fsgsbase/64: Introduce FS/GS base helper functions Chang S. Bae
2018-06-06 16:23 ` [PATCH v2 2/8] x86/fsgsbase/64: Make ptrace read FS/GS base accurately Chang S. Bae
2018-06-06 16:23 ` [PATCH v2 3/8] x86/fsgsbase/64: Use FS/GS base helpers in core dump Chang S. Bae
2018-06-06 16:23 ` [PATCH v2 4/8] x86/fsgsbase/64: Factor out load FS/GS segments from __switch_to Chang S. Bae
2018-06-06 16:23 ` [PATCH v2 5/8] x86/msr: write_rdtscp_aux() to use wrmsr_safe() Chang S. Bae
2018-06-06 17:11 ` Andy Lutomirski
2018-06-06 16:23 ` [PATCH v2 6/8] x86/segments/64: Rename PER_CPU segment to CPU_NUMBER Chang S. Bae
2018-06-06 17:16 ` Andy Lutomirski
2018-06-06 16:23 ` Chang S. Bae [this message]
2018-06-06 17:16 ` [PATCH v2 7/8] x86/segments/32: Introduce CPU_NUMBER segment Andy Lutomirski
2018-06-06 19:07 ` Brian Gerst
2018-06-06 19:24 ` Andy Lutomirski
2018-06-06 22:53 ` hpa
2018-06-06 16:23 ` [PATCH v2 8/8] x86/vdso: Move out the CPU number store Chang S. Bae
2018-06-06 17:25 ` Andy Lutomirski
2018-06-06 18:27 ` Bae, Chang Seok
2018-06-06 22:59 ` Bae, Chang Seok
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