[PATCH 0/5] i.MX8MQ support for GPCv2 irqchip driver

[PATCH 0/5] i.MX8MQ support for GPCv2 irqchip driver

[Andrey Smirnov]

Everyone:

This series is 4 trivial (and optional) changes and a patch to add
support for i.MX8MQ to GPCv2 irqchip driver. Bingings for new GPC
variant were taken from [gpcv2-imx8mq]. Hopefully all of the patches
are self-explanatory.

Feedback is welcome!

Thanks,
Andrey Smrinov

[gpcv2-imx8mq] https://lore.kernel.org/linux-arm-kernel/20181116154927.16152-3-l.stach@pengutronix.de/

Andrey Smirnov (5):
  irqchip/irq-imx-gpcv2: Remove unused code
  irqchip/irq-imx-gpcv2: Share reg offset calculation code
  irqchip/irq-imx-gpcv2: Make use of BIT() macro
  irqchip/irq-imx-gpcv2: Make error messages more consistent
  irqchip/irq-imx-gpcv2: Add support for i.MX8MQ

 drivers/irqchip/irq-imx-gpcv2.c | 61 ++++++++++++++++++++++++---------
 1 file changed, 44 insertions(+), 17 deletions(-)

-- 
2.19.1

[PATCH 1/5] irqchip/irq-imx-gpcv2: Remove unused code

[Andrey Smirnov]

Varaible 'reg' in imx_gpcv2_irq_set_wake() has no users. Remove it.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/irqchip/irq-imx-gpcv2.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 4760307ab43f..cbed00319315 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -73,11 +73,9 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
 	struct gpcv2_irqchip_data *cd = d->chip_data;
 	unsigned int idx = d->hwirq / 32;
 	unsigned long flags;
-	void __iomem *reg;
 	u32 mask, val;
 
 	raw_spin_lock_irqsave(&cd->rlock, flags);
-	reg = cd->gpc_base + cd->cpu2wakeup + idx * 4;
 	mask = 1 << d->hwirq % 32;
 	val = cd->wakeup_sources[idx];
 
-- 
2.19.1

[PATCH 2/5] irqchip/irq-imx-gpcv2: Share reg offset calculation code

[Andrey Smirnov]

Move identical offset calculation code into a small helper function
and make use of it in the rest of the code.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/irqchip/irq-imx-gpcv2.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index cbed00319315..b262ba8b2652 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -28,6 +28,11 @@ struct gpcv2_irqchip_data {
 
 static struct gpcv2_irqchip_data *imx_gpcv2_instance;
 
+static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
+{
+	return cd->gpc_base + cd->cpu2wakeup + i * 4;
+}
+
 static int gpcv2_wakeup_source_save(void)
 {
 	struct gpcv2_irqchip_data *cd;
@@ -39,7 +44,7 @@ static int gpcv2_wakeup_source_save(void)
 		return 0;
 
 	for (i = 0; i < IMR_NUM; i++) {
-		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
+		reg = gpcv2_idx_to_reg(cd, i);
 		cd->saved_irq_mask[i] = readl_relaxed(reg);
 		writel_relaxed(cd->wakeup_sources[i], reg);
 	}
@@ -50,17 +55,14 @@ static int gpcv2_wakeup_source_save(void)
 static void gpcv2_wakeup_source_restore(void)
 {
 	struct gpcv2_irqchip_data *cd;
-	void __iomem *reg;
 	int i;
 
 	cd = imx_gpcv2_instance;
 	if (!cd)
 		return;
 
-	for (i = 0; i < IMR_NUM; i++) {
-		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
-		writel_relaxed(cd->saved_irq_mask[i], reg);
-	}
+	for (i = 0; i < IMR_NUM; i++)
+		writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
 }
 
 static struct syscore_ops imx_gpcv2_syscore_ops = {
@@ -97,7 +99,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
 	u32 val;
 
 	raw_spin_lock(&cd->rlock);
-	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
+	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
 	val = readl_relaxed(reg);
 	val &= ~(1 << d->hwirq % 32);
 	writel_relaxed(val, reg);
@@ -113,7 +115,7 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
 	u32 val;
 
 	raw_spin_lock(&cd->rlock);
-	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
+	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
 	val = readl_relaxed(reg);
 	val |= 1 << (d->hwirq % 32);
 	writel_relaxed(val, reg);
-- 
2.19.1

[PATCH 3/5] irqchip/irq-imx-gpcv2: Make use of BIT() macro

[Andrey Smirnov]

Convert all instances of 1 << x to BIT(x) for consistency with other
kernel code.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/irqchip/irq-imx-gpcv2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index b262ba8b2652..077d56b3183a 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -78,7 +78,7 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
 	u32 mask, val;
 
 	raw_spin_lock_irqsave(&cd->rlock, flags);
-	mask = 1 << d->hwirq % 32;
+	mask = BIT(d->hwirq % 32);
 	val = cd->wakeup_sources[idx];
 
 	cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
@@ -101,7 +101,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
 	raw_spin_lock(&cd->rlock);
 	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
 	val = readl_relaxed(reg);
-	val &= ~(1 << d->hwirq % 32);
+	val &= ~BIT(d->hwirq % 32);
 	writel_relaxed(val, reg);
 	raw_spin_unlock(&cd->rlock);
 
@@ -117,7 +117,7 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
 	raw_spin_lock(&cd->rlock);
 	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
 	val = readl_relaxed(reg);
-	val |= 1 << (d->hwirq % 32);
+	val |= BIT(d->hwirq % 32);
 	writel_relaxed(val, reg);
 	raw_spin_unlock(&cd->rlock);
 
-- 
2.19.1

[PATCH 4/5] irqchip/irq-imx-gpcv2: Make error messages more consistent

[Andrey Smirnov]

Make error messages more consistent by making sure each starts with
"%pOF:".

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/irqchip/irq-imx-gpcv2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 077d56b3183a..c2b2b3128ddd 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -212,7 +212,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 
 	cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
 	if (!cd) {
-		pr_err("kzalloc failed!\n");
+		pr_err("%pOF: kzalloc failed!\n", node);
 		return -ENOMEM;
 	}
 
@@ -220,7 +220,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 
 	cd->gpc_base = of_iomap(node, 0);
 	if (!cd->gpc_base) {
-		pr_err("fsl-gpcv2: unable to map gpc registers\n");
+		pr_err("%pOF: unable to map gpc registers\n", node);
 		kfree(cd);
 		return -ENOMEM;
 	}
-- 
2.19.1

[PATCH 5/5] irqchip/irq-imx-gpcv2: Add support for i.MX8MQ

[Andrey Smirnov]

Add code needed to support i.MX8MQ.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/irqchip/irq-imx-gpcv2.c | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index c2b2b3128ddd..17a2dad2d4c2 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -17,6 +17,9 @@
 
 #define GPC_IMR1_CORE0		0x30
 #define GPC_IMR1_CORE1		0x40
+#define GPC_IMR1_CORE2		0x1c0
+#define GPC_IMR1_CORE3		0x1d0
+
 
 struct gpcv2_irqchip_data {
 	struct raw_spinlock	rlock;
@@ -192,11 +195,19 @@ static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
 	.free		= irq_domain_free_irqs_common,
 };
 
+static const struct of_device_id gpcv2_of_match[] = {
+	{ .compatible = "fsl,imx7d-gpc",  .data = (const void *) 2 },
+	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
+	{ /* END */ }
+};
+
 static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 			       struct device_node *parent)
 {
 	struct irq_domain *parent_domain, *domain;
 	struct gpcv2_irqchip_data *cd;
+	const struct of_device_id *id;
+	unsigned long core_num;
 	int i;
 
 	if (!parent) {
@@ -204,6 +215,14 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 		return -ENODEV;
 	}
 
+	id = of_match_node(gpcv2_of_match, node);
+	if (!id) {
+		pr_err("%pOF: unknown compatibility string\n", node);
+		return -ENODEV;
+	}
+
+	core_num = (unsigned long)id->data;
+
 	parent_domain = irq_find_host(parent);
 	if (!parent_domain) {
 		pr_err("%pOF: unable to get parent domain\n", node);
@@ -236,8 +255,16 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 
 	/* Initially mask all interrupts */
 	for (i = 0; i < IMR_NUM; i++) {
-		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
-		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
+		void __iomem *reg = cd->gpc_base + i * 4;
+
+		switch (core_num) {
+		case 4:
+			writel_relaxed(~0, reg + GPC_IMR1_CORE2);
+			writel_relaxed(~0, reg + GPC_IMR1_CORE3);
+		case 2:	      /* FALLTHROUGH */
+			writel_relaxed(~0, reg + GPC_IMR1_CORE0);
+			writel_relaxed(~0, reg + GPC_IMR1_CORE1);
+		}
 		cd->wakeup_sources[i] = ~0;
 	}
 
-- 
2.19.1

Re: [PATCH 1/5] irqchip/irq-imx-gpcv2: Remove unused code

[Lucas Stach]

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Varaible 'reg' in imx_gpcv2_irq_set_wake() has no users. Remove it.
> 
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: cphealy@gmail.com
> Cc: l.stach@pengutronix.de
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/irqchip/irq-imx-gpcv2.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
> index 4760307ab43f..cbed00319315 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -73,11 +73,9 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
> >  	struct gpcv2_irqchip_data *cd = d->chip_data;
> >  	unsigned int idx = d->hwirq / 32;
> >  	unsigned long flags;
> > -	void __iomem *reg;
> >  	u32 mask, val;
>  
> >  	raw_spin_lock_irqsave(&cd->rlock, flags);
> > -	reg = cd->gpc_base + cd->cpu2wakeup + idx * 4;
> >  	mask = 1 << d->hwirq % 32;
> >  	val = cd->wakeup_sources[idx];
>  

Re: [PATCH 2/5] irqchip/irq-imx-gpcv2: Share reg offset calculation code

[Lucas Stach]

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Move identical offset calculation code into a small helper function
> and make use of it in the rest of the code.
> 
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: cphealy@gmail.com
> Cc: l.stach@pengutronix.de
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Nice cleanup!

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/irqchip/irq-imx-gpcv2.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
> index cbed00319315..b262ba8b2652 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -28,6 +28,11 @@ struct gpcv2_irqchip_data {
>  
>  static struct gpcv2_irqchip_data *imx_gpcv2_instance;
>  
> +static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
> +{
> > +	return cd->gpc_base + cd->cpu2wakeup + i * 4;
> +}
> +
>  static int gpcv2_wakeup_source_save(void)
>  {
> >  	struct gpcv2_irqchip_data *cd;
> @@ -39,7 +44,7 @@ static int gpcv2_wakeup_source_save(void)
> >  		return 0;
>  
> >  	for (i = 0; i < IMR_NUM; i++) {
> > -		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
> > +		reg = gpcv2_idx_to_reg(cd, i);
> >  		cd->saved_irq_mask[i] = readl_relaxed(reg);
> >  		writel_relaxed(cd->wakeup_sources[i], reg);
> >  	}
> @@ -50,17 +55,14 @@ static int gpcv2_wakeup_source_save(void)
>  static void gpcv2_wakeup_source_restore(void)
>  {
> >  	struct gpcv2_irqchip_data *cd;
> > -	void __iomem *reg;
> >  	int i;
>  
> >  	cd = imx_gpcv2_instance;
> >  	if (!cd)
> >  		return;
>  
> > -	for (i = 0; i < IMR_NUM; i++) {
> > -		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
> > -		writel_relaxed(cd->saved_irq_mask[i], reg);
> > -	}
> > +	for (i = 0; i < IMR_NUM; i++)
> > +		writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
>  }
>  
>  static struct syscore_ops imx_gpcv2_syscore_ops = {
> @@ -97,7 +99,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
> >  	u32 val;
>  
> >  	raw_spin_lock(&cd->rlock);
> > -	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
> > +	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
> >  	val = readl_relaxed(reg);
> >  	val &= ~(1 << d->hwirq % 32);
> >  	writel_relaxed(val, reg);
> @@ -113,7 +115,7 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
> >  	u32 val;
>  
> >  	raw_spin_lock(&cd->rlock);
> > -	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
> > +	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
> >  	val = readl_relaxed(reg);
> >  	val |= 1 << (d->hwirq % 32);
> >  	writel_relaxed(val, reg);

Re: [PATCH 3/5] irqchip/irq-imx-gpcv2: Make use of BIT() macro

[Lucas Stach]

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Convert all instances of 1 << x to BIT(x) for consistency with other
> kernel code.
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: cphealy@gmail.com
> Cc: l.stach@pengutronix.de
> Cc: Leonard Crestez <leonard.crestez@nxp.com>
> Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/irqchip/irq-imx-gpcv2.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-
> imx-gpcv2.c
> index b262ba8b2652..077d56b3183a 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -78,7 +78,7 @@ static int imx_gpcv2_irq_set_wake(struct irq_data
> *d, unsigned int on)
>  	u32 mask, val;
>  
>  	raw_spin_lock_irqsave(&cd->rlock, flags);
> -	mask = 1 << d->hwirq % 32;
> +	mask = BIT(d->hwirq % 32);
>  	val = cd->wakeup_sources[idx];
>  
>  	cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
> @@ -101,7 +101,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data
> *d)
>  	raw_spin_lock(&cd->rlock);
>  	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
>  	val = readl_relaxed(reg);
> -	val &= ~(1 << d->hwirq % 32);
> +	val &= ~BIT(d->hwirq % 32);
>  	writel_relaxed(val, reg);
>  	raw_spin_unlock(&cd->rlock);
>  
> @@ -117,7 +117,7 @@ static void imx_gpcv2_irq_mask(struct irq_data
> *d)
>  	raw_spin_lock(&cd->rlock);
>  	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
>  	val = readl_relaxed(reg);
> -	val |= 1 << (d->hwirq % 32);
> +	val |= BIT(d->hwirq % 32);
>  	writel_relaxed(val, reg);
>  	raw_spin_unlock(&cd->rlock);
>  

Re: [PATCH 4/5] irqchip/irq-imx-gpcv2: Make error messages more consistent

[Lucas Stach]

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Make error messages more consistent by making sure each starts with
> "%pOF:".
> 
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: cphealy@gmail.com
> Cc: l.stach@pengutronix.de
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/irqchip/irq-imx-gpcv2.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
> index 077d56b3183a..c2b2b3128ddd 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -212,7 +212,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
>  
> >  	cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
> >  	if (!cd) {
> > -		pr_err("kzalloc failed!\n");
> > +		pr_err("%pOF: kzalloc failed!\n", node);
> >  		return -ENOMEM;
> >  	}
>  
> @@ -220,7 +220,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
>  
> >  	cd->gpc_base = of_iomap(node, 0);
> >  	if (!cd->gpc_base) {
> > -		pr_err("fsl-gpcv2: unable to map gpc registers\n");
> > +		pr_err("%pOF: unable to map gpc registers\n", node);
> >  		kfree(cd);
> >  		return -ENOMEM;
> >  	}

Re: [PATCH 5/5] irqchip/irq-imx-gpcv2: Add support for i.MX8MQ

[Lucas Stach]

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Add code needed to support i.MX8MQ.
> 
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: cphealy@gmail.com
> Cc: l.stach@pengutronix.de
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  drivers/irqchip/irq-imx-gpcv2.c | 31 +++++++++++++++++++++++++++++--
>  1 file changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
> index c2b2b3128ddd..17a2dad2d4c2 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -17,6 +17,9 @@
>  
> >  #define GPC_IMR1_CORE0		0x30
> >  #define GPC_IMR1_CORE1		0x40
> > +#define GPC_IMR1_CORE2		0x1c0
> > +#define GPC_IMR1_CORE3		0x1d0
> +
>  
>  struct gpcv2_irqchip_data {
> > >  	struct raw_spinlock	rlock;
> @@ -192,11 +195,19 @@ static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
> > >  	.free		= irq_domain_free_irqs_common,
>  };
>  
> +static const struct of_device_id gpcv2_of_match[] = {
> > +	{ .compatible = "fsl,imx7d-gpc",  .data = (const void *) 2 },
> > +	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
> > +	{ /* END */ }
> +};
> +
>  static int __init imx_gpcv2_irqchip_init(struct device_node *node,
> >  			       struct device_node *parent)
>  {
> >  	struct irq_domain *parent_domain, *domain;
> >  	struct gpcv2_irqchip_data *cd;
> > +	const struct of_device_id *id;
> > +	unsigned long core_num;
> >  	int i;
>  
> >  	if (!parent) {
> @@ -204,6 +215,14 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
> >  		return -ENODEV;
> >  	}
>  
> > +	id = of_match_node(gpcv2_of_match, node);
> > +	if (!id) {
> > +		pr_err("%pOF: unknown compatibility string\n", node);
> > +		return -ENODEV;
> > +	}
> +
> > +	core_num = (unsigned long)id->data;
> +
> >  	parent_domain = irq_find_host(parent);
> >  	if (!parent_domain) {
> >  		pr_err("%pOF: unable to get parent domain\n", node);
> @@ -236,8 +255,16 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
>  
> >  	/* Initially mask all interrupts */
> >  	for (i = 0; i < IMR_NUM; i++) {
> > -		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
> > -		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
> > +		void __iomem *reg = cd->gpc_base + i * 4;
> +
> > +		switch (core_num) {
> > +		case 4:
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE2);
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE3);
> > > +		case 2:	      /* FALLTHROUGH */
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE0);
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE1);
> +		}

The writes being not being in linear descending core order does trigger
something in me, but obviously this doesn't has any effect on the code,
so:

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

>  		cd->wakeup_sources[i] = ~0;
> >  	}
>  

Re: [PATCH 0/5] i.MX8MQ support for GPCv2 irqchip driver

[Marc Zyngier]

On 06/12/2018 07:31, Andrey Smirnov wrote:
> Everyone:
> 
> This series is 4 trivial (and optional) changes and a patch to add
> support for i.MX8MQ to GPCv2 irqchip driver. Bingings for new GPC
> variant were taken from [gpcv2-imx8mq]. Hopefully all of the patches
> are self-explanatory.
> 
> Feedback is welcome!
> 
> Thanks,
> Andrey Smrinov
> 
> [gpcv2-imx8mq] https://lore.kernel.org/linux-arm-kernel/20181116154927.16152-3-l.stach@pengutronix.de/
> 
> Andrey Smirnov (5):
>   irqchip/irq-imx-gpcv2: Remove unused code
>   irqchip/irq-imx-gpcv2: Share reg offset calculation code
>   irqchip/irq-imx-gpcv2: Make use of BIT() macro
>   irqchip/irq-imx-gpcv2: Make error messages more consistent
>   irqchip/irq-imx-gpcv2: Add support for i.MX8MQ
> 
>  drivers/irqchip/irq-imx-gpcv2.c | 61 ++++++++++++++++++++++++---------
>  1 file changed, 44 insertions(+), 17 deletions(-)
> 

I've queued this for 4.21.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...