[PATCH 0/2] Bug Fixes to Tap Delay code in SDHCI Arasan driver

[PATCH 0/2] Bug Fixes to Tap Delay code in SDHCI Arasan driver

[Manish Narani]

This patch set consists a couple of minor bug fixes for SDHCI Arasan
driver. The fixes are for tap delay programming where in some cases
tuning is failing for some of the SD cards.

Manish Narani (2):
  mmc: sdhci-of-arasan: Use Mask writes for Tap delays
  mmc: sdhci-of-arasan: Issue DLL reset explicitly

 drivers/mmc/host/sdhci-of-arasan.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

-- 
2.17.1

[PATCH 1/2] mmc: sdhci-of-arasan: Use Mask writes for Tap delays

[Manish Narani]

Mask the ITAP and OTAP delay bits before updating with the new
tap value for Versal platform.

Fixes: 1a470721c8f5 ("sdhci: arasan: Add support for Versal Tap Delays")
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/mmc/host/sdhci-of-arasan.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 100621e55427..3ec5ecad637c 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -30,7 +30,10 @@
 #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
 
 #define SDHCI_ARASAN_ITAPDLY_REGISTER	0xF0F8
+#define SDHCI_ARASAN_ITAPDLY_SEL_MASK	0xFF
+
 #define SDHCI_ARASAN_OTAPDLY_REGISTER	0xF0FC
+#define SDHCI_ARASAN_OTAPDLY_SEL_MASK	0x3F
 
 #define SDHCI_ARASAN_CQE_BASE_ADDR	0x200
 #define VENDOR_ENHANCED_STROBE		BIT(0)
@@ -755,6 +758,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
 		regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 		regval |= SDHCI_OTAPDLY_ENABLE;
 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
+		regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 		regval |= tap_delay;
 		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 	}
@@ -822,6 +826,7 @@ static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 		regval |= SDHCI_ITAPDLY_ENABLE;
 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
+		regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 		regval |= tap_delay;
 		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 		regval &= ~SDHCI_ITAPDLY_CHGWIN;
-- 
2.17.1

Re: [PATCH 1/2] mmc: sdhci-of-arasan: Use Mask writes for Tap delays

[Michal Simek]

On 16. 11. 20 7:15, Manish Narani wrote:
> Mask the ITAP and OTAP delay bits before updating with the new
> tap value for Versal platform.
> 
> Fixes: 1a470721c8f5 ("sdhci: arasan: Add support for Versal Tap Delays")
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 100621e55427..3ec5ecad637c 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -30,7 +30,10 @@
>  #define SDHCI_ARASAN_VENDOR_REGISTER	0x78
>  
>  #define SDHCI_ARASAN_ITAPDLY_REGISTER	0xF0F8
> +#define SDHCI_ARASAN_ITAPDLY_SEL_MASK	0xFF
> +
>  #define SDHCI_ARASAN_OTAPDLY_REGISTER	0xF0FC
> +#define SDHCI_ARASAN_OTAPDLY_SEL_MASK	0x3F
>  
>  #define SDHCI_ARASAN_CQE_BASE_ADDR	0x200
>  #define VENDOR_ENHANCED_STROBE		BIT(0)
> @@ -755,6 +758,7 @@ static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
>  		regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
>  		regval |= SDHCI_OTAPDLY_ENABLE;
>  		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
> +		regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
>  		regval |= tap_delay;
>  		sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
>  	}
> @@ -822,6 +826,7 @@ static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
>  		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
>  		regval |= SDHCI_ITAPDLY_ENABLE;
>  		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
> +		regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
>  		regval |= tap_delay;
>  		sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
>  		regval &= ~SDHCI_ITAPDLY_CHGWIN;
> 

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

[PATCH 2/2] mmc: sdhci-of-arasan: Issue DLL reset explicitly

[Manish Narani]

In the current implementation DLL reset will be issued for
each ITAP and OTAP setting inside ATF, this is creating issues
in some scenarios and this sequence is not inline with the TRM.
To fix the issue, DLL reset should be removed from the ATF and
host driver will request it explicitly.
This patch update host driver to explicitly request for DLL reset
before ITAP (assert DLL) and after OTAP (release DLL) settings.

Fixes: a5c8b2ae2e51 ("mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup")
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 drivers/mmc/host/sdhci-of-arasan.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 3ec5ecad637c..e066d8f51954 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -635,6 +635,9 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
 	if (ret)
 		pr_err("Error setting Output Tap Delay\n");
 
+	eemi_ops->ioctl(node_id, IOCTL_SD_DLL_RESET,
+			PM_DLL_RESET_RELEASE, 0, NULL);
+
 	return ret;
 }
 
@@ -794,6 +797,9 @@ static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
 	if (host->version < SDHCI_SPEC_300)
 		return 0;
 
+	eemi_ops->ioctl(node_id, IOCTL_SD_DLL_RESET,
+			PM_DLL_RESET_ASSERT, 0, NULL);
+
 	switch (host->timing) {
 	case MMC_TIMING_MMC_HS:
 	case MMC_TIMING_SD_HS:
-- 
2.17.1

Re: [PATCH 2/2] mmc: sdhci-of-arasan: Issue DLL reset explicitly

[Michal Simek]

On 16. 11. 20 7:15, Manish Narani wrote:
> In the current implementation DLL reset will be issued for
> each ITAP and OTAP setting inside ATF, this is creating issues
> in some scenarios and this sequence is not inline with the TRM.
> To fix the issue, DLL reset should be removed from the ATF and
> host driver will request it explicitly.
> This patch update host driver to explicitly request for DLL reset
> before ITAP (assert DLL) and after OTAP (release DLL) settings.
> 
> Fixes: a5c8b2ae2e51 ("mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup")
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 3ec5ecad637c..e066d8f51954 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -635,6 +635,9 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
>  	if (ret)
>  		pr_err("Error setting Output Tap Delay\n");
>  
> +	eemi_ops->ioctl(node_id, IOCTL_SD_DLL_RESET,
> +			PM_DLL_RESET_RELEASE, 0, NULL);
> +
>  	return ret;
>  }
>  
> @@ -794,6 +797,9 @@ static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
>  	if (host->version < SDHCI_SPEC_300)
>  		return 0;
>  
> +	eemi_ops->ioctl(node_id, IOCTL_SD_DLL_RESET,
> +			PM_DLL_RESET_ASSERT, 0, NULL);
> +
>  	switch (host->timing) {
>  	case MMC_TIMING_MMC_HS:
>  	case MMC_TIMING_SD_HS:
> 

this won't apply. It needs to be fixed.

Thanks,
Michal