From: Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Conor Dooley <conor@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Borislav Petkov <bp@alien8.de>, Tony Luck <tony.luck@intel.com>,
Conor Dooley <conor+dt@kernel.org>,
Abel Vesa <abelvesa@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: cache: qcom,llcc: allow optional second interrupt for LCP/SRP ECC
Date: Wed, 21 Oct 2026 17:17:44 +0530 [thread overview]
Message-ID: <162c8c6d-800b-46f5-92e4-3a5501ff9d12@oss.qualcomm.com> (raw)
In-Reply-To: <20261017-shaggy-funny-pogona-69fe36@quoll>
On 17-10-2026 22:04, Krzysztof Kozlowski wrote:
> On Wed, Oct 14, 2026 at 09:26:16PM +0530, Faiyaz Mohammed wrote:
>> QCM2390 (Shikra) has an LCP/SRP block that signals DDR DRAM ECC errors
>> on a dedicated interrupt line separate from the existing TRP/DRP cache
>> ECC interrupt.
>>
>> Allow an optional second interrupt in the LLCC binding, add
>> interrupt-names with "llcc-ecc" and "llcc-lcp-ecc", and enforce both
>> are present when compatible is qcom,shikra-llcc.
>>
>> Signed-off-by: Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/cache/qcom,llcc.yaml | 26 +++++++++++++++++++++-
>> 1 file changed, 25 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> index 2141e5d4de63..3546cf7c2519 100644
>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> @@ -64,7 +64,17 @@ properties:
>> maxItems: 18
>>
>> interrupts:
>> - maxItems: 1
>> + minItems: 1
>> + items:
>> + - description: TRP/DRP LLCC cache ECC (ddrss_apps_interrupt[2])
>> + - description: LCP/SRP DDR DRAM ECC (ddrss_apps_interrupt[1]), present
>> + on platforms with an LCP/SRP block such as QCM2390
>> +
>> + interrupt-names:
>> + minItems: 1
>> + items:
>> + - const: llcc-ecc
>
> ecc
>
>> + - const: llcc-lcp-ecc
>
> lcp
>
Done — renamed to "ecc" and "lcp" in both the binding and the Shikra
DTS node. Also addressing the Sashiko finding in the same patch: added
an else clause restoring maxItems: 1 for all non-Shikra platforms.
>>
>> memory-region:
>> maxItems: 1
>> @@ -234,6 +244,20 @@ allOf:
>> - const: llcc1_base
>> - const: llcc_broadcast_base
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: qcom,shikra-llcc
>> + then:
>> + properties:
>> + interrupts:
>> + minItems: 2
>> + interrupt-names:
>> + minItems: 2
>> + required:
>> + - interrupt-names
>
> Please address other comments/emails.
>
Done.
> Best regards,
> Krzysztof
Thanks & regards,
Mohammed Faiyaz
next prev parent reply other threads:[~2026-10-21 11:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 15:56 [PATCH 0/4] edac: qcom: add DDR DRAM ECC reporting for Shikra (QCM2390) Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 1/4] dt-bindings: cache: qcom,llcc: allow optional second interrupt for LCP/SRP ECC Faiyaz Mohammed
2026-10-17 16:34 ` Krzysztof Kozlowski
2026-10-21 11:47 ` Faiyaz Mohammed [this message]
2026-10-14 15:56 ` [PATCH 2/4] soc: qcom: llcc: add LCP/SRP DDR DRAM ECC register offsets Faiyaz Mohammed
2026-10-16 17:20 ` Jonathan Cameron
2026-10-21 11:49 ` Faiyaz Mohammed
2026-10-17 16:34 ` Krzysztof Kozlowski
2026-10-21 11:54 ` Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 3/4] edac: qcom: add LCP/SRP DDR DRAM ECC support for Shikra Faiyaz Mohammed
2026-10-16 17:26 ` Jonathan Cameron
2026-10-21 12:01 ` Faiyaz Mohammed
2026-10-14 15:56 ` [PATCH 4/4] arm64: dts: qcom: shikra: add LCP/SRP ECC interrupt to LLCC node Faiyaz Mohammed
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