[PATCH v2 0/8] Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform

[PATCH v2 0/8] Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to add initial support for Renesas RZ/V2H(P) SoC
and GP-EVK platform. Support for below peripherals is enabled on
RZ/V2H GP-EVK platform:
- RIIC
- OSTM
- SDHI
- WDT

patch #1 and #2 depends on
1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240724094707.569596-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

patch #3, #4, #5 and #7 depends on
1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240805193846.52416-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

patch #6 and #8 depends on
1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240805193846.52416-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
2] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240806210623.183842-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (8):
  arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC
  arm64: dts: renesas: Add initial DTS for RZ/V2H GP-EVK board
  arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes
  arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes
  arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes
  arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
  arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
  arm64: dts: renesas: r9a09g057h44-gp-evk: Enable watchdog

 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    | 532 ++++++++++++++++++
 .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 256 +++++++++
 3 files changed, 790 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts

-- 
2.34.1

[PATCH v2 1/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are
the list of blocks added:
- EXT CLKs
- 4X CA55
- SCIF
- PFC
- CPG
- SYS
- GIC
- ARMv8 Timer

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- Updated commit description
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++++++
 1 file changed, 165 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
new file mode 100644
index 000000000000..cf890026e284
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2H(P) SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g057";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	audio_extal_clk: audio-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	rtxin_clk: rtxin-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	qextal_clk: qextal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		pinctrl: pinctrl@10410000 {
+			compatible = "renesas,r9a09g057-pinctrl";
+			reg = <0 0x10410000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 96>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			power-domains = <&cpg>;
+			resets = <&cpg 165>, <&cpg 166>;
+		};
+
+		cpg: clock-controller@10420000 {
+			compatible = "renesas,r9a09g057-cpg";
+			reg = <0 0x10420000 0 0x10000>;
+			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+			clock-names = "audio_extal", "rtxin", "qextal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sys: system-controller@10430000 {
+			compatible = "renesas,r9a09g057-sys";
+			reg = <0 0x10430000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>;
+			resets = <&cpg 48>;
+			status = "disabled";
+		};
+
+		scif: serial@11c01400 {
+			compatible = "renesas,scif-r9a09g057";
+			reg = <0 0x11c01400 0 0x400>;
+			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+					  "tei", "tei-dri", "rxi-edge", "txi-edge";
+			clocks = <&cpg CPG_MOD 143>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg 149>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@14900000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0x14900000 0 0x20000>,
+			      <0x0 0x14940000 0 0x80000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
-- 
2.34.1

[PATCH v2 2/8] arm64: dts: renesas: Add initial DTS for RZ/V2H GP-EVK board

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add initial DTS for RZ/V2H GP-EVK board, adding the below support:
- Memory
- Clock inputs
- PINCTRL
- SCIF

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- No change.
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 61 +++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index fbd214a1a638..b2249a2710aa 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -137,5 +137,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-gp-evk.dtb
+
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
new file mode 100644
index 000000000000..593c48181248
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2H GP-EVK board
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g057.dtsi"
+
+/ {
+	model = "Renesas GP-EVK Board based on r9a09g057h44";
+	compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
+
+	aliases {
+		serial0 = &scif;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x1 0xF8000000>;
+	};
+
+	memory@240000000 {
+		device_type = "memory";
+		reg = <0x2 0x40000000 0x2 0x00000000>;
+	};
+};
+
+&audio_extal_clk {
+	clock-frequency = <22579200>;
+};
+
+&pinctrl {
+	scif_pins: scif {
+		pins = "SCIF_TXD", "SCIF_RXD";
+		renesas,output-impedance = <1>;
+	};
+};
+
+&qextal_clk {
+	clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+	clock-frequency = <32768>;
+};
+
+&scif {
+	pinctrl-0 = <&scif_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
-- 
2.34.1

[PATCH v2 3/8] arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add OSTM0-OSTM7 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 80 ++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index cf890026e284..3d6c3a604ec9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -121,6 +121,26 @@ sys: system-controller@10430000 {
 			status = "disabled";
 		};
 
+		ostm0: timer@11800000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x11800000 0x0 0x1000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 67>;
+			resets = <&cpg 109>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ostm1: timer@11801000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x11801000 0x0 0x1000>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 68>;
+			resets = <&cpg 110>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		scif: serial@11c01400 {
 			compatible = "renesas,scif-r9a09g057";
 			reg = <0 0x11c01400 0 0x400>;
@@ -142,6 +162,66 @@ scif: serial@11c01400 {
 			status = "disabled";
 		};
 
+		ostm4: timer@12c00000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x12c00000 0x0 0x1000>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 71>;
+			resets = <&cpg 113>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ostm5: timer@12c01000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x12c01000 0x0 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 72>;
+			resets = <&cpg 114>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ostm6: timer@12c02000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x12c02000 0x0 0x1000>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 73>;
+			resets = <&cpg 115>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ostm7: timer@12c03000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x12c03000 0x0 0x1000>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 74>;
+			resets = <&cpg 116>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ostm2: timer@14000000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x14000000 0x0 0x1000>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 69>;
+			resets = <&cpg 111>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ostm3: timer@14001000 {
+			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
+			reg = <0x0 0x14001000 0x0 0x1000>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD 70>;
+			resets = <&cpg 112>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@14900000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
-- 
2.34.1

[PATCH v2 4/8] arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add RIIC0-RIIC8 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 198 +++++++++++++++++++++
 1 file changed, 198 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 3d6c3a604ec9..c9e1e21b820d 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -141,6 +141,28 @@ ostm1: timer@11801000 {
 			status = "disabled";
 		};
 
+		i2c8: i2c@11c01000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x11c01000 0 0x400>;
+			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 147>;
+			clock-frequency = <100000>;
+			resets = <&cpg 160>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		scif: serial@11c01400 {
 			compatible = "renesas,scif-r9a09g057";
 			reg = <0 0x11c01400 0 0x400>;
@@ -222,6 +244,182 @@ ostm3: timer@14001000 {
 			status = "disabled";
 		};
 
+		i2c0: i2c@14400400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14400400 0 0x400>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 148>;
+			clock-frequency = <100000>;
+			resets = <&cpg 152>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@14400800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14400800 0 0x400>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 149>;
+			clock-frequency = <100000>;
+			resets = <&cpg 153>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@14400c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14400c00 0 0x400>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 150>;
+			clock-frequency = <100000>;
+			resets = <&cpg 154>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@14401000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14401000 0 0x400>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 151>;
+			clock-frequency = <100000>;
+			resets = <&cpg 155>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@14401400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14401400 0 0x400>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 152>;
+			clock-frequency = <100000>;
+			resets = <&cpg 156>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@14401800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14401800 0 0x400>;
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 153>;
+			clock-frequency = <100000>;
+			resets = <&cpg 157>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@14401c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14401c00 0 0x400>;
+			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 154>;
+			clock-frequency = <100000>;
+			resets = <&cpg 158>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@14402000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,riic-r9a09g057";
+			reg = <0 0x14402000 0 0x400>;
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 155>;
+			clock-frequency = <100000>;
+			resets = <&cpg 159>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@14900000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
-- 
2.34.1

[PATCH v2 5/8] arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add SDHI0-SDHI2 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 45 ++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index c9e1e21b820d..435b1f4e7d38 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -429,6 +429,51 @@ gic: interrupt-controller@14900000 {
 			      <0x0 0x14940000 0 0x80000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
+
+		sdhi0: mmc@15c00000  {
+			compatible = "renesas,sdhi-r9a09g057";
+			reg = <0x0 0x15c00000 0 0x10000>;
+			interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 163>,
+				 <&cpg CPG_MOD 165>,
+				 <&cpg CPG_MOD 164>,
+				 <&cpg CPG_MOD 166>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg 167>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sdhi1: mmc@15c10000 {
+			compatible = "renesas,sdhi-r9a09g057";
+			reg = <0x0 0x15c10000 0 0x10000>;
+			interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 167>,
+				 <&cpg CPG_MOD 169>,
+				 <&cpg CPG_MOD 168>,
+				 <&cpg CPG_MOD 170>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg 168>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sdhi2: mmc@15c20000 {
+			compatible = "renesas,sdhi-r9a09g057";
+			reg = <0x0 0x15c20000 0 0x10000>;
+			interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 171>,
+				 <&cpg CPG_MOD 173>,
+				 <&cpg CPG_MOD 172>,
+				 <&cpg CPG_MOD 174>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg 169>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
 	};
 
 	timer {
-- 
2.34.1

[PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 435b1f4e7d38..7f4e8ad9b0a5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -184,6 +184,17 @@ scif: serial@11c01400 {
 			status = "disabled";
 		};
 
+		wdt0: watchdog@11c00400 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x11c00400 0 0x400>;
+			clocks = <&cpg CPG_MOD 75>,
+				 <&cpg CPG_MOD 76>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 117>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		ostm4: timer@12c00000 {
 			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
 			reg = <0x0 0x12c00000 0x0 0x1000>;
@@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
 			status = "disabled";
 		};
 
+		wdt2: watchdog@13000000 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x13000000 0 0x400>;
+			clocks = <&cpg CPG_MOD 79>,
+				 <&cpg CPG_MOD 80>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 119>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@13000400 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x13000400 0 0x400>;
+			clocks = <&cpg CPG_MOD 81>,
+				 <&cpg CPG_MOD 82>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 120>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		ostm2: timer@14000000 {
 			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
 			reg = <0x0 0x14000000 0x0 0x1000>;
@@ -244,6 +277,17 @@ ostm3: timer@14001000 {
 			status = "disabled";
 		};
 
+		wdt1: watchdog@14400000 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x14400000 0 0x400>;
+			clocks = <&cpg CPG_MOD 77>,
+				 <&cpg CPG_MOD 78>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 118>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@14400400 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.34.1

[PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2
connector) on the RZ/V2H GP-EVK platform.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 191 ++++++++++++++++++
 1 file changed, 191 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
index 593c48181248..11c13c85d278 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
@@ -7,6 +7,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "r9a09g057.dtsi"
 
 / {
@@ -14,6 +16,14 @@ / {
 	compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
 
 	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		mmc1 = &sdhi1;
 		serial0 = &scif;
 	};
 
@@ -32,17 +42,186 @@ memory@240000000 {
 		device_type = "memory";
 		reg = <0x2 0x40000000 0x2 0x00000000>;
 	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vqmmc_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+		regulator-name = "SDHI1 VccQ";
+		gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		gpios-states = <0>;
+		states = <3300000 0>, <1800000 1>;
+	};
 };
 
 &audio_extal_clk {
 	clock-frequency = <22579200>;
 };
 
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-0 = <&i2c3_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&i2c6 {
+	pinctrl-0 = <&i2c6_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&i2c7 {
+	pinctrl-0 = <&i2c7_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&i2c8 {
+	pinctrl-0 = <&i2c8_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+&ostm1 {
+	status = "okay";
+};
+
+&ostm2 {
+	status = "okay";
+};
+
+&ostm3 {
+	status = "okay";
+};
+
+&ostm4 {
+	status = "okay";
+};
+
+&ostm5 {
+	status = "okay";
+};
+
+&ostm6 {
+	status = "okay";
+};
+
+&ostm7 {
+	status = "okay";
+};
+
 &pinctrl {
+	i2c0_pins: i2c0 {
+		pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
+			 <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
+	};
+
+	i2c1_pins: i2c1 {
+		pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
+			 <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
+	};
+
+	i2c2_pins: i2c2 {
+		pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
+			 <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
+	};
+
+	i2c3_pins: i2c3 {
+		pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
+			 <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
+	};
+
+	i2c6_pins: i2c6 {
+		pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
+			 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
+	};
+
+	i2c7_pins: i2c7 {
+		pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
+			 <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
+	};
+
+	i2c8_pins: i2c8 {
+		pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
+			 <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
+	};
+
 	scif_pins: scif {
 		pins = "SCIF_TXD", "SCIF_RXD";
 		renesas,output-impedance = <1>;
 	};
+
+	sd1-pwr-en-hog {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "sd1_pwr_en";
+	};
+
+	sdhi1_pins: sd1 {
+		sd1_data {
+			pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3";
+			input-enable;
+			renesas,output-impedance = <3>;
+			slew-rate = <1>;
+		};
+
+		sd1_cmd {
+			pins = "SD1CMD";
+			input-enable;
+			renesas,output-impedance = <3>;
+			slew-rate = <1>;
+		};
+
+		sd1_clk {
+			pins = "SD1CLK";
+			renesas,output-impedance = <3>;
+			slew-rate = <1>;
+		};
+
+		sd1_cd {
+			pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
+		};
+	};
 };
 
 &qextal_clk {
@@ -59,3 +238,15 @@ &scif {
 
 	status = "okay";
 };
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-1 = <&sdhi1_pins>;
+	pinctrl-names = "default", "state_uhs";
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&vqmmc_sdhi1>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
-- 
2.34.1

[PATCH v2 8/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable watchdog

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable WDT1 watchdog on RZ/V2H GP-EVK platform.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
index 11c13c85d278..e6befb1d638f 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
@@ -250,3 +250,7 @@ &sdhi1 {
 	sd-uhs-sdr104;
 	status = "okay";
 };
+
+&wdt1 {
+	status = "okay";
+};
-- 
2.34.1

RE: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI

[Biju Das]

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Sunday, August 11, 2024 9:50 PM
> Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2
> connector) on the RZ/V2H GP-EVK platform.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - New patch
> ---
>  .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 191 ++++++++++++++++++
>  1 file changed, 191 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> index 593c48181248..11c13c85d278 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> @@ -7,6 +7,8 @@
> 
>  /dts-v1/;
> 
> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> +#include <dt-bindings/gpio/gpio.h>
>  #include "r9a09g057.dtsi"
> 
>  / {
> @@ -14,6 +16,14 @@ / {
>  	compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
> 
>  	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
> +		i2c8 = &i2c8;
> +		mmc1 = &sdhi1;
>  		serial0 = &scif;
>  	};
> 
> @@ -32,17 +42,186 @@ memory@240000000 {
>  		device_type = "memory";
>  		reg = <0x2 0x40000000 0x2 0x00000000>;
>  	};
> +
> +	reg_3p3v: regulator1 {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "fixed-3.3V";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	vqmmc_sdhi1: regulator-vccq-sdhi1 {
> +		compatible = "regulator-gpio";
> +		regulator-name = "SDHI1 VccQ";
> +		gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpios-states = <0>;
> +		states = <3300000 0>, <1800000 1>;
> +	};
>  };
> 
>  &audio_extal_clk {
>  	clock-frequency = <22579200>;
>  };
> 
> +&i2c0 {
> +	pinctrl-0 = <&i2c0_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +

clock-frequency = <100000>; in SoC dtsim

Why frequency set to 100kHz for all the i2c nodes even though SoC supports
Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz? 

Cheers,
Biju


> +&i2c1 {
> +	pinctrl-0 = <&i2c1_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	pinctrl-0 = <&i2c2_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&i2c3 {
> +	pinctrl-0 = <&i2c3_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&i2c6 {
> +	pinctrl-0 = <&i2c6_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&i2c7 {
> +	pinctrl-0 = <&i2c7_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&i2c8 {
> +	pinctrl-0 = <&i2c8_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&ostm0 {
> +	status = "okay";
> +};
> +
> +&ostm1 {
> +	status = "okay";
> +};
> +
> +&ostm2 {
> +	status = "okay";
> +};
> +
> +&ostm3 {
> +	status = "okay";
> +};
> +
> +&ostm4 {
> +	status = "okay";
> +};
> +
> +&ostm5 {
> +	status = "okay";
> +};
> +
> +&ostm6 {
> +	status = "okay";
> +};
> +
> +&ostm7 {
> +	status = "okay";
> +};
> +
>  &pinctrl {
> +	i2c0_pins: i2c0 {
> +		pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
> +			 <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
> +	};
> +
> +	i2c1_pins: i2c1 {
> +		pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
> +			 <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
> +	};
> +
> +	i2c2_pins: i2c2 {
> +		pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
> +			 <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
> +	};
> +
> +	i2c3_pins: i2c3 {
> +		pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
> +			 <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
> +	};
> +
> +	i2c6_pins: i2c6 {
> +		pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
> +			 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
> +	};
> +
> +	i2c7_pins: i2c7 {
> +		pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
> +			 <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
> +	};
> +
> +	i2c8_pins: i2c8 {
> +		pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
> +			 <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
> +	};
> +
>  	scif_pins: scif {
>  		pins = "SCIF_TXD", "SCIF_RXD";
>  		renesas,output-impedance = <1>;
>  	};
> +
> +	sd1-pwr-en-hog {
> +		gpio-hog;
> +		gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
> +		output-high;
> +		line-name = "sd1_pwr_en";
> +	};
> +
> +	sdhi1_pins: sd1 {
> +		sd1_data {
> +			pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3";
> +			input-enable;
> +			renesas,output-impedance = <3>;
> +			slew-rate = <1>;
> +		};
> +
> +		sd1_cmd {
> +			pins = "SD1CMD";
> +			input-enable;
> +			renesas,output-impedance = <3>;
> +			slew-rate = <1>;
> +		};
> +
> +		sd1_clk {
> +			pins = "SD1CLK";
> +			renesas,output-impedance = <3>;
> +			slew-rate = <1>;
> +		};
> +
> +		sd1_cd {
> +			pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
> +		};
> +	};
>  };
> 
>  &qextal_clk {
> @@ -59,3 +238,15 @@ &scif {
> 
>  	status = "okay";
>  };
> +
> +&sdhi1 {
> +	pinctrl-0 = <&sdhi1_pins>;
> +	pinctrl-1 = <&sdhi1_pins>;
> +	pinctrl-names = "default", "state_uhs";
> +	vmmc-supply = <&reg_3p3v>;
> +	vqmmc-supply = <&vqmmc_sdhi1>;
> +	bus-width = <4>;
> +	sd-uhs-sdr50;
> +	sd-uhs-sdr104;
> +	status = "okay";
> +};
> --
> 2.34.1

Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI

[Lad, Prabhakar]

Hi Biju,

On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Sunday, August 11, 2024 9:50 PM
> > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2
> > connector) on the RZ/V2H GP-EVK platform.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - New patch
> > ---
> >  .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 191 ++++++++++++++++++
> >  1 file changed, 191 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > index 593c48181248..11c13c85d278 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > @@ -7,6 +7,8 @@
> >
> >  /dts-v1/;
> >
> > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > +#include <dt-bindings/gpio/gpio.h>
> >  #include "r9a09g057.dtsi"
> >
> >  / {
> > @@ -14,6 +16,14 @@ / {
> >       compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
> >
> >       aliases {
> > +             i2c0 = &i2c0;
> > +             i2c1 = &i2c1;
> > +             i2c2 = &i2c2;
> > +             i2c3 = &i2c3;
> > +             i2c6 = &i2c6;
> > +             i2c7 = &i2c7;
> > +             i2c8 = &i2c8;
> > +             mmc1 = &sdhi1;
> >               serial0 = &scif;
> >       };
> >
> > @@ -32,17 +42,186 @@ memory@240000000 {
> >               device_type = "memory";
> >               reg = <0x2 0x40000000 0x2 0x00000000>;
> >       };
> > +
> > +     reg_3p3v: regulator1 {
> > +             compatible = "regulator-fixed";
> > +
> > +             regulator-name = "fixed-3.3V";
> > +             regulator-min-microvolt = <3300000>;
> > +             regulator-max-microvolt = <3300000>;
> > +             regulator-boot-on;
> > +             regulator-always-on;
> > +     };
> > +
> > +     vqmmc_sdhi1: regulator-vccq-sdhi1 {
> > +             compatible = "regulator-gpio";
> > +             regulator-name = "SDHI1 VccQ";
> > +             gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
> > +             regulator-min-microvolt = <1800000>;
> > +             regulator-max-microvolt = <3300000>;
> > +             gpios-states = <0>;
> > +             states = <3300000 0>, <1800000 1>;
> > +     };
> >  };
> >
> >  &audio_extal_clk {
> >       clock-frequency = <22579200>;
> >  };
> >
> > +&i2c0 {
> > +     pinctrl-0 = <&i2c0_pins>;
> > +     pinctrl-names = "default";
> > +
> > +     status = "okay";
> > +};
> > +
>
> clock-frequency = <100000>; in SoC dtsim
>
> Why frequency set to 100kHz for all the i2c nodes even though SoC supports
> Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz?
>
This is due to driver limitation, once driver support for FM+ gets
accepted [0] I plan to update the default frequency to !MHz in SoC
DTSI.

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240711115207.2843133-9-claudiu.beznea.uj@bp.renesas.com/

Cheers,
Prabhakar

RE: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Monday, August 12, 2024 10:16 AM
> Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
> 
> Hi Biju,
> 
> On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Sunday, August 11, 2024 9:50 PM
> > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk:
> > > Enable OSTM, I2C, and SDHI
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the
> > > SD2
> > > connector) on the RZ/V2H GP-EVK platform.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - New patch
> > > ---
> > >  .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 191
> > > ++++++++++++++++++
> > >  1 file changed, 191 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > index 593c48181248..11c13c85d278 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > @@ -7,6 +7,8 @@
> > >
> > >  /dts-v1/;
> > >
> > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > > +#include <dt-bindings/gpio/gpio.h>
> > >  #include "r9a09g057.dtsi"
> > >
> > >  / {
> > > @@ -14,6 +16,14 @@ / {
> > >       compatible = "renesas,gp-evk", "renesas,r9a09g057h44",
> > > "renesas,r9a09g057";
> > >
> > >       aliases {
> > > +             i2c0 = &i2c0;
> > > +             i2c1 = &i2c1;
> > > +             i2c2 = &i2c2;
> > > +             i2c3 = &i2c3;
> > > +             i2c6 = &i2c6;
> > > +             i2c7 = &i2c7;
> > > +             i2c8 = &i2c8;
> > > +             mmc1 = &sdhi1;
> > >               serial0 = &scif;
> > >       };
> > >
> > > @@ -32,17 +42,186 @@ memory@240000000 {
> > >               device_type = "memory";
> > >               reg = <0x2 0x40000000 0x2 0x00000000>;
> > >       };
> > > +
> > > +     reg_3p3v: regulator1 {
> > > +             compatible = "regulator-fixed";
> > > +
> > > +             regulator-name = "fixed-3.3V";
> > > +             regulator-min-microvolt = <3300000>;
> > > +             regulator-max-microvolt = <3300000>;
> > > +             regulator-boot-on;
> > > +             regulator-always-on;
> > > +     };
> > > +
> > > +     vqmmc_sdhi1: regulator-vccq-sdhi1 {
> > > +             compatible = "regulator-gpio";
> > > +             regulator-name = "SDHI1 VccQ";
> > > +             gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
> > > +             regulator-min-microvolt = <1800000>;
> > > +             regulator-max-microvolt = <3300000>;
> > > +             gpios-states = <0>;
> > > +             states = <3300000 0>, <1800000 1>;
> > > +     };
> > >  };
> > >
> > >  &audio_extal_clk {
> > >       clock-frequency = <22579200>;
> > >  };
> > >
> > > +&i2c0 {
> > > +     pinctrl-0 = <&i2c0_pins>;
> > > +     pinctrl-names = "default";
> > > +
> > > +     status = "okay";
> > > +};
> > > +
> >
> > clock-frequency = <100000>; in SoC dtsim
> >
> > Why frequency set to 100kHz for all the i2c nodes even though SoC
> > supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz?
> >
> This is due to driver limitation, once driver support for FM+ gets accepted [0] I plan to update the
> default frequency to !MHz in SoC DTSI.

If there os no board limitation, please update to 400kHz, that is the next best frequency.

Cheers,
Biju

> 
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240711115207.2843133-9-
> claudiu.beznea.uj@bp.renesas.com/
> 
> Cheers,
> Prabhakar

RE: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Sunday, August 11, 2024 9:50 PM
> Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - New patch
> ---
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> index 435b1f4e7d38..7f4e8ad9b0a5 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -184,6 +184,17 @@ scif: serial@11c01400 {
>  			status = "disabled";
>  		};
> 
> +		wdt0: watchdog@11c00400 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x11c00400 0 0x400>;
> +			clocks = <&cpg CPG_MOD 75>,
> +				 <&cpg CPG_MOD 76>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 117>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +
>  		ostm4: timer@12c00000 {
>  			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
>  			reg = <0x0 0x12c00000 0x0 0x1000>;
> @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
>  			status = "disabled";
>  		};
> 
> +		wdt2: watchdog@13000000 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x13000000 0 0x400>;
> +			clocks = <&cpg CPG_MOD 79>,
> +				 <&cpg CPG_MOD 80>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 119>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};

I guess same group(all wdt together) arranged together?? Not sure.

Cheers,
Biju

> +
> +		wdt3: watchdog@13000400 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x13000400 0 0x400>;
> +			clocks = <&cpg CPG_MOD 81>,
> +				 <&cpg CPG_MOD 82>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 120>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +
>  		ostm2: timer@14000000 {
>  			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
>  			reg = <0x0 0x14000000 0x0 0x1000>;
> @@ -244,6 +277,17 @@ ostm3: timer@14001000 {
>  			status = "disabled";
>  		};
> 
> +		wdt1: watchdog@14400000 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x14400000 0 0x400>;
> +			clocks = <&cpg CPG_MOD 77>,
> +				 <&cpg CPG_MOD 78>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 118>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@14400400 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> --
> 2.34.1

Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI

[Lad, Prabhakar]

Hi Biju,

On Mon, Aug 12, 2024 at 11:02 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Monday, August 12, 2024 10:16 AM
> > Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
> >
> > Hi Biju,
> >
> > On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Sunday, August 11, 2024 9:50 PM
> > > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk:
> > > > Enable OSTM, I2C, and SDHI
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the
> > > > SD2
> > > > connector) on the RZ/V2H GP-EVK platform.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > - New patch
> > > > ---
> > > >  .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 191
> > > > ++++++++++++++++++
> > > >  1 file changed, 191 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > index 593c48181248..11c13c85d278 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > @@ -7,6 +7,8 @@
> > > >
> > > >  /dts-v1/;
> > > >
> > > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > >  #include "r9a09g057.dtsi"
> > > >
> > > >  / {
> > > > @@ -14,6 +16,14 @@ / {
> > > >       compatible = "renesas,gp-evk", "renesas,r9a09g057h44",
> > > > "renesas,r9a09g057";
> > > >
> > > >       aliases {
> > > > +             i2c0 = &i2c0;
> > > > +             i2c1 = &i2c1;
> > > > +             i2c2 = &i2c2;
> > > > +             i2c3 = &i2c3;
> > > > +             i2c6 = &i2c6;
> > > > +             i2c7 = &i2c7;
> > > > +             i2c8 = &i2c8;
> > > > +             mmc1 = &sdhi1;
> > > >               serial0 = &scif;
> > > >       };
> > > >
> > > > @@ -32,17 +42,186 @@ memory@240000000 {
> > > >               device_type = "memory";
> > > >               reg = <0x2 0x40000000 0x2 0x00000000>;
> > > >       };
> > > > +
> > > > +     reg_3p3v: regulator1 {
> > > > +             compatible = "regulator-fixed";
> > > > +
> > > > +             regulator-name = "fixed-3.3V";
> > > > +             regulator-min-microvolt = <3300000>;
> > > > +             regulator-max-microvolt = <3300000>;
> > > > +             regulator-boot-on;
> > > > +             regulator-always-on;
> > > > +     };
> > > > +
> > > > +     vqmmc_sdhi1: regulator-vccq-sdhi1 {
> > > > +             compatible = "regulator-gpio";
> > > > +             regulator-name = "SDHI1 VccQ";
> > > > +             gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
> > > > +             regulator-min-microvolt = <1800000>;
> > > > +             regulator-max-microvolt = <3300000>;
> > > > +             gpios-states = <0>;
> > > > +             states = <3300000 0>, <1800000 1>;
> > > > +     };
> > > >  };
> > > >
> > > >  &audio_extal_clk {
> > > >       clock-frequency = <22579200>;
> > > >  };
> > > >
> > > > +&i2c0 {
> > > > +     pinctrl-0 = <&i2c0_pins>;
> > > > +     pinctrl-names = "default";
> > > > +
> > > > +     status = "okay";
> > > > +};
> > > > +
> > >
> > > clock-frequency = <100000>; in SoC dtsim
> > >
> > > Why frequency set to 100kHz for all the i2c nodes even though SoC
> > > supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz?
> > >
> > This is due to driver limitation, once driver support for FM+ gets accepted [0] I plan to update the
> > default frequency to !MHz in SoC DTSI.
>
> If there os no board limitation, please update to 400kHz, that is the next best frequency.
>
I'll let Geert take a call on this as anyway the once the patch [0]
will be merged we will update frequency to 1MHz.

> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240711115207.2843133-9-
> > claudiu.beznea.uj@bp.renesas.com/
> >
Cheers,
Prabhakar

Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Lad, Prabhakar]

Hi Biju,

On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Sunday, August 11, 2024 9:50 PM
> > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - New patch
> > ---
> >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> >                       status = "disabled";
> >               };
> >
> > +             wdt0: watchdog@11c00400 {
> > +                     compatible = "renesas,r9a09g057-wdt";
> > +                     reg = <0 0x11c00400 0 0x400>;
> > +                     clocks = <&cpg CPG_MOD 75>,
> > +                              <&cpg CPG_MOD 76>;
> > +                     clock-names = "pclk", "oscclk";
> > +                     resets = <&cpg 117>;
> > +                     power-domains = <&cpg>;
> > +                     status = "disabled";
> > +             };
> > +
> >               ostm4: timer@12c00000 {
> >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> >                       reg = <0x0 0x12c00000 0x0 0x1000>;
> > @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
> >                       status = "disabled";
> >               };
> >
> > +             wdt2: watchdog@13000000 {
> > +                     compatible = "renesas,r9a09g057-wdt";
> > +                     reg = <0 0x13000000 0 0x400>;
> > +                     clocks = <&cpg CPG_MOD 79>,
> > +                              <&cpg CPG_MOD 80>;
> > +                     clock-names = "pclk", "oscclk";
> > +                     resets = <&cpg 119>;
> > +                     power-domains = <&cpg>;
> > +                     status = "disabled";
> > +             };
>
> I guess same group(all wdt together) arranged together?? Not sure.
>
I think Geert prefers it to be sorted based on unit address. So I'll
let Geert make a decision on this (and the rest of the similar patches
where nodes are sorted based on unit address and not grouped based on
IP).

Cheers,
Prabhakar

RE: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Biju Das]

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Monday, August 12, 2024 1:32 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm <magnus.damm@gmail.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Fabrizio
> Castro <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> Subject: Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> 
> Hi Biju,
> 
> On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Sunday, August 11, 2024 9:50 PM
> > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add
> > > WDT0-WDT3 nodes
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - New patch
> > > ---
> > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44
> > > ++++++++++++++++++++++
> > >  1 file changed, 44 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt0: watchdog@11c00400 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x11c00400 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 75>,
> > > +                              <&cpg CPG_MOD 76>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 117>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > >               ostm4: timer@12c00000 {
> > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > >                       reg = <0x0 0x12c00000 0x0 0x1000>; @@ -224,6
> > > +235,28 @@ ostm7: timer@12c03000 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt2: watchdog@13000000 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x13000000 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 79>,
> > > +                              <&cpg CPG_MOD 80>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 119>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> >
> > I guess same group(all wdt together) arranged together?? Not sure.
> >
> I think Geert prefers it to be sorted based on unit address. So I'll let Geert make a decision on this
> (and the rest of the similar patches where nodes are sorted based on unit address and not grouped
> based on IP).

I agree. If that is the case we need to fix [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a774a1.dtsi?h=next-20240812#n584
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a77960.dtsi?h=next-20240812#n633

Cheers,
Biju

RE: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Biju Das]

> -----Original Message-----
> From: Biju Das
> Sent: Monday, August 12, 2024 1:40 PM
> To: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm <magnus.damm@gmail.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Fabrizio
> Castro <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> Subject: RE: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> 
> 
> 
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Monday, August 12, 2024 1:32 PM
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof
> > Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> > linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org;
> > linux-kernel@vger.kernel.org; Fabrizio Castro
> > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad
> > <prabhakar.mahadev- lad.rj@bp.renesas.com>
> > Subject: Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add
> > WDT0-WDT3 nodes
> >
> > Hi Biju,
> >
> > On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Sunday, August 11, 2024 9:50 PM
> > > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add
> > > > WDT0-WDT3 nodes
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > - New patch
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44
> > > > ++++++++++++++++++++++
> > > >  1 file changed, 44 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt0: watchdog@11c00400 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x11c00400 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 75>,
> > > > +                              <&cpg CPG_MOD 76>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 117>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > >               ostm4: timer@12c00000 {
> > > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > > >                       reg = <0x0 0x12c00000 0x0 0x1000>; @@ -224,6
> > > > +235,28 @@ ostm7: timer@12c03000 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt2: watchdog@13000000 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x13000000 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 79>,
> > > > +                              <&cpg CPG_MOD 80>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 119>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > >
> > > I guess same group(all wdt together) arranged together?? Not sure.
> > >
> > I think Geert prefers it to be sorted based on unit address. So I'll
> > let Geert make a decision on this (and the rest of the similar patches
> > where nodes are sorted based on unit address and not grouped based on IP).
> 
> I agree. If that is the case we need to fix [1] [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/tree/arch/arm64/boot/dts/renesas/r8a774a1.dtsi?h=next-20240812#n584
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/tree/arch/arm64/boot/dts/renesas/r8a77960.dtsi?h=next-20240812#n633

Similarly 

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a77960.dtsi?h=next-20240812#n762

Cheers,
Biju

RE: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Monday, August 12, 2024 1:29 PM
> Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
> 
> Hi Biju,
> 
> On Mon, Aug 12, 2024 at 11:02 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Monday, August 12, 2024 10:16 AM
> > > Subject: Re: [PATCH v2 7/8] arm64: dts: renesas:
> > > r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
> > >
> > > Hi Biju,
> > >
> > > On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Thanks for the patch.
> > > >
> > > > > -----Original Message-----
> > > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > > Sent: Sunday, August 11, 2024 9:50 PM
> > > > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk:
> > > > > Enable OSTM, I2C, and SDHI
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on
> > > > > the
> > > > > SD2
> > > > > connector) on the RZ/V2H GP-EVK platform.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v1->v2
> > > > > - New patch
> > > > > ---
> > > > >  .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 191
> > > > > ++++++++++++++++++
> > > > >  1 file changed, 191 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > > index 593c48181248..11c13c85d278 100644
> > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> > > > > @@ -7,6 +7,8 @@
> > > > >
> > > > >  /dts-v1/;
> > > > >
> > > > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > > > > +#include <dt-bindings/gpio/gpio.h>
> > > > >  #include "r9a09g057.dtsi"
> > > > >
> > > > >  / {
> > > > > @@ -14,6 +16,14 @@ / {
> > > > >       compatible = "renesas,gp-evk", "renesas,r9a09g057h44",
> > > > > "renesas,r9a09g057";
> > > > >
> > > > >       aliases {
> > > > > +             i2c0 = &i2c0;
> > > > > +             i2c1 = &i2c1;
> > > > > +             i2c2 = &i2c2;
> > > > > +             i2c3 = &i2c3;
> > > > > +             i2c6 = &i2c6;
> > > > > +             i2c7 = &i2c7;
> > > > > +             i2c8 = &i2c8;
> > > > > +             mmc1 = &sdhi1;
> > > > >               serial0 = &scif;
> > > > >       };
> > > > >
> > > > > @@ -32,17 +42,186 @@ memory@240000000 {
> > > > >               device_type = "memory";
> > > > >               reg = <0x2 0x40000000 0x2 0x00000000>;
> > > > >       };
> > > > > +
> > > > > +     reg_3p3v: regulator1 {
> > > > > +             compatible = "regulator-fixed";
> > > > > +
> > > > > +             regulator-name = "fixed-3.3V";
> > > > > +             regulator-min-microvolt = <3300000>;
> > > > > +             regulator-max-microvolt = <3300000>;
> > > > > +             regulator-boot-on;
> > > > > +             regulator-always-on;
> > > > > +     };
> > > > > +
> > > > > +     vqmmc_sdhi1: regulator-vccq-sdhi1 {
> > > > > +             compatible = "regulator-gpio";
> > > > > +             regulator-name = "SDHI1 VccQ";
> > > > > +             gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
> > > > > +             regulator-min-microvolt = <1800000>;
> > > > > +             regulator-max-microvolt = <3300000>;
> > > > > +             gpios-states = <0>;
> > > > > +             states = <3300000 0>, <1800000 1>;
> > > > > +     };
> > > > >  };
> > > > >
> > > > >  &audio_extal_clk {
> > > > >       clock-frequency = <22579200>;  };
> > > > >
> > > > > +&i2c0 {
> > > > > +     pinctrl-0 = <&i2c0_pins>;
> > > > > +     pinctrl-names = "default";
> > > > > +
> > > > > +     status = "okay";
> > > > > +};
> > > > > +
> > > >
> > > > clock-frequency = <100000>; in SoC dtsim
> > > >
> > > > Why frequency set to 100kHz for all the i2c nodes even though SoC
> > > > supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz?
> > > >
> > > This is due to driver limitation, once driver support for FM+ gets
> > > accepted [0] I plan to update the default frequency to !MHz in SoC DTSI.
> >
> > If there os no board limitation, please update to 400kHz, that is the next best frequency.
> >
> I'll let Geert take a call on this as anyway the once the patch [0] will be merged we will update
> frequency to 1MHz.

OK. Please make sure you don't set 1MHz for some devices like OV5645 which has a max transfer speed 400kHz.

Cheers,
Biju

> 
> > > [0]
> > > https://patchwork.kernel.org/project/linux-renesas-soc/patch/2024071
> > > 1115207.2843133-9-
> > > claudiu.beznea.uj@bp.renesas.com/
> > >
> Cheers,
> Prabhakar

Re: [PATCH v2 0/8] Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform

[Rob Herring (Arm)]

On Sun, 11 Aug 2024 21:49:47 +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This patch series aims to add initial support for Renesas RZ/V2H(P) SoC
> and GP-EVK platform. Support for below peripherals is enabled on
> RZ/V2H GP-EVK platform:
> - RIIC
> - OSTM
> - SDHI
> - WDT
> 
> patch #1 and #2 depends on
> 1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240724094707.569596-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> 
> patch #3, #4, #5 and #7 depends on
> 1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240805193846.52416-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> 
> patch #6 and #8 depends on
> 1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240805193846.52416-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> 2] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240806210623.183842-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> 
> Cheers,
> Prabhakar
> 
> Lad Prabhakar (8):
>   arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC
>   arm64: dts: renesas: Add initial DTS for RZ/V2H GP-EVK board
>   arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes
>   arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes
>   arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes
>   arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
>   arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI
>   arm64: dts: renesas: r9a09g057h44-gp-evk: Enable watchdog
> 
>  arch/arm64/boot/dts/renesas/Makefile          |   2 +
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi    | 532 ++++++++++++++++++
>  .../boot/dts/renesas/r9a09g057h44-gp-evk.dts  | 256 +++++++++
>  3 files changed, 790 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057.dtsi
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts
> 
> --
> 2.34.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y renesas/r9a09g057h44-gp-evk.dtb' for 20240811204955.270231-1-prabhakar.mahadev-lad.rj@bp.renesas.com:

arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed:
	['renesas,gp-evk', 'renesas,r9a09g057h44', 'renesas,r9a09g057'] is too long
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed:
		['renesas,gp-evk', 'renesas,r9a09g057h44', 'renesas,r9a09g057'] is too short
		'shimafuji,kingfisher' was expected
		'renesas,r9a09g057h44' is not one of ['renesas,h3ulcb', 'renesas,m3ulcb', 'renesas,m3nulcb']
		'renesas,r9a09g057' is not one of ['renesas,r8a7795', 'renesas,r8a7796', 'renesas,r8a77961', 'renesas,r8a77965']
		'renesas,r9a09g057' is not one of ['renesas,r8a779m0', 'renesas,r8a779m1', 'renesas,r8a779m2', 'renesas,r8a779m3', 'renesas,r8a779m4', 'renesas,r8a779m5', 'renesas,r8a779m8', 'renesas,r8a779mb']
	'renesas,gp-evk' is not one of ['renesas,kzm9d']
	'renesas,gp-evk' is not one of ['renesas,genmai', 'renesas,gr-peach', 'renesas,rskrza1']
	'renesas,gp-evk' is not one of ['renesas,rza2mevb']
	'renesas,gp-evk' is not one of ['renesas,kzm9g']
	'renesas,gp-evk' is not one of ['renesas,ape6evm']
	'renesas,gp-evk' is not one of ['renesas,armadillo800eva']
	'renesas,gp-evk' is not one of ['iwave,g21m']
	'renesas,gp-evk' is not one of ['iwave,g21d']
	'renesas,gp-evk' is not one of ['iwave,g20d']
	'renesas,gp-evk' is not one of ['iwave,g20m', 'renesas,sk-rzg1m']
	'renesas,gp-evk' is not one of ['iwave,g20m']
	'renesas,gp-evk' is not one of ['iwave,g22m', 'renesas,sk-rzg1e']
	'iwave,g22d' was expected
	'renesas,gp-evk' is not one of ['iwave,g23s']
	'renesas,gp-evk' is not one of ['hoperun,hihope-rzg2m', 'beacon,beacon-rzg2m']
	'renesas,gp-evk' is not one of ['hoperun,hihope-rzg2-ex']
	'renesas,gp-evk' is not one of ['hoperun,hihope-rzg2m']
	'renesas,gp-evk' is not one of ['beacon,beacon-rzg2n', 'hoperun,hihope-rzg2n']
	'renesas,gp-evk' is not one of ['si-linux,cat874']
	'renesas,gp-evk' is not one of ['si-linux,cat875']
	'renesas,gp-evk' is not one of ['beacon,beacon-rzg2h', 'hoperun,hihope-rzg2h']
	'renesas,gp-evk' is not one of ['renesas,bockw']
	'renesas,gp-evk' is not one of ['renesas,marzen']
	'renesas,gp-evk' is not one of ['renesas,lager', 'renesas,stout']
	'renesas,gp-evk' is not one of ['renesas,henninger', 'renesas,koelsch', 'renesas,porter']
	'renesas,gp-evk' is not one of ['renesas,blanche', 'renesas,wheat']
	'renesas,gp-evk' is not one of ['renesas,gose']
	'renesas,gp-evk' is not one of ['renesas,alt', 'renesas,silk']
	'renesas,gp-evk' is not one of ['renesas,h3ulcb', 'renesas,salvator-x', 'renesas,salvator-xs']
	'renesas,gp-evk' is not one of ['renesas,m3ulcb', 'renesas,salvator-x', 'renesas,salvator-xs']
	'renesas,gp-evk' is not one of ['renesas,m3ulcb', 'renesas,salvator-xs']
	'renesas,gp-evk' is not one of ['renesas,m3nulcb', 'renesas,salvator-x', 'renesas,salvator-xs']
	'renesas,gp-evk' is not one of ['renesas,eagle', 'renesas,v3msk']
	'renesas,gp-evk' is not one of ['renesas,condor', 'renesas,v3hsk']
	'renesas,gp-evk' is not one of ['renesas,condor-i']
	'renesas,gp-evk' is not one of ['renesas,ebisu']
	'renesas,gp-evk' is not one of ['renesas,draak']
	'renesas,gp-evk' is not one of ['renesas,falcon-cpu']
	'renesas,gp-evk' is not one of ['renesas,falcon-breakout']
	'renesas,gp-evk' is not one of ['renesas,spider-cpu']
	'renesas,gp-evk' is not one of ['renesas,spider-breakout']
	'renesas,gp-evk' is not one of ['renesas,s4sk']
	'renesas,gp-evk' is not one of ['renesas,white-hawk-cpu']
	'renesas,gp-evk' is not one of ['renesas,white-hawk-single']
	'renesas,gp-evk' is not one of ['renesas,white-hawk-breakout']
	'renesas,gp-evk' is not one of ['renesas,gray-hawk-single']
	'renesas,gp-evk' is not one of ['renesas,h3ulcb', 'renesas,salvator-xs']
	'renesas,gp-evk' is not one of ['renesas,m3nulcb', 'renesas,salvator-xs']
	'renesas,gp-evk' is not one of ['renesas,rzn1d400-db']
	'renesas,gp-evk' is not one of ['renesas,rzn1d400-eb']
	'renesas,gp-evk' is not one of ['renesas,smarc-evk']
	'renesas,gp-evk' is not one of ['renesas,r9a08g045s33']
	'renesas,rzg3s-smarcm' was expected
	'renesas,smarc2-evk' was expected
	'renesas,gp-evk' is not one of ['renesas,rzv2mevk2']
	'renesas,gp-evk' is not one of ['renesas,r9a09g057h41', 'renesas,r9a09g057h42', 'renesas,r9a09g057h44']
	'renesas,emev2' was expected
	'renesas,r7s72100' was expected
	'renesas,r7s9210' was expected
	'renesas,sh73a0' was expected
	'renesas,r8a73a4' was expected
	'renesas,r8a7740' was expected
	'renesas,r8a7742' was expected
	'iwave,g21m' was expected
	'iwave,g20m' was expected
	'renesas,r8a7743' was expected
	'renesas,r8a7744' was expected
	'renesas,r8a7745' was expected
	'iwave,g22m' was expected
	'renesas,r8a77470' was expected
	'renesas,r8a774a1' was expected
	'hoperun,hihope-rzg2m' was expected
	'renesas,r8a774a3' was expected
	'renesas,r8a774b1' was expected
	'hoperun,hihope-rzg2n' was expected
	'renesas,r8a774c0' was expected
	'si-linux,cat874' was expected
	'renesas,r8a774e1' was expected
	'hoperun,hihope-rzg2h' was expected
	'renesas,r8a7778' was expected
	'renesas,r8a7779' was expected
	'renesas,r8a7790' was expected
	'renesas,r8a7791' was expected
	'renesas,r8a7792' was expected
	'renesas,r8a7793' was expected
	'renesas,r8a7794' was expected
	'renesas,r8a7795' was expected
	'renesas,r8a7796' was expected
	'renesas,r8a77961' was expected
	'renesas,r8a77965' was expected
	'renesas,r8a77970' was expected
	'renesas,r8a77980' was expected
	'renesas,r8a77980a' was expected
	'renesas,r8a77990' was expected
	'renesas,r8a77995' was expected
	'renesas,r8a779a0' was expected
	'renesas,falcon-cpu' was expected
	'renesas,r8a779f0' was expected
	'renesas,spider-cpu' was expected
	'renesas,r8a779f4' was expected
	'renesas,r8a779g0' was expected
	'renesas,r8a779g2' was expected
	'renesas,white-hawk-cpu' was expected
	'renesas,r8a779h0' was expected
	'renesas,r8a779m0' was expected
	'renesas,r8a779m1' was expected
	'renesas,r8a779m2' was expected
	'renesas,r8a779m3' was expected
	'renesas,r8a779m4' was expected
	'renesas,r8a779m5' was expected
	'renesas,r8a779m6' was expected
	'renesas,r8a779m7' was expected
	'renesas,r8a779m8' was expected
	'renesas,r8a779mb' was expected
	'renesas,r9a06g032' was expected
	'renesas,rzn1d400-db' was expected
	'renesas,r9a09g057h44' is not one of ['renesas,r9a07g043f01', 'renesas,r9a07g043u11', 'renesas,r9a07g043u12']
	'renesas,r9a09g057h44' is not one of ['renesas,r9a07g044c1', 'renesas,r9a07g044c2', 'renesas,r9a07g044l1', 'renesas,r9a07g044l2']
	'renesas,r9a09g057h44' is not one of ['renesas,r9a07g054l1', 'renesas,r9a07g054l2']
	'renesas,r9a08g045' was expected
	'renesas,r9a08g045s33' was expected
	'renesas,r9a09g011' was expected
	'renesas,r9a09g057' was expected
	'renesas,r9a07g043' was expected
	'renesas,r9a07g044' was expected
	'renesas,r9a07g054' was expected
	from schema $id: http://devicetree.org/schemas/soc/renesas/renesas.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: /: compatible:0: 'anyOf' conditional failed, one must be fixed:
	'renesas,gp-evk' does not match '^renesas,(emev2|r(7s|8a|9a)[a-z0-9]+|rcar|rmobile|rz[a-z0-9]*|sh(7[a-z0-9]+)?|mobile)-[a-z0-9-]+$'
	'renesas,gp-evk' does not match '^renesas,(condor|falcon|gr-peach|gray-hawk|salvator|sk-rz|smar(c(2)?)?|spider|white-hawk)(.*)?$'
	'renesas,gp-evk' does not match '^renesas,(can|cpg|dmac|du|(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq]spi|rcar_sound|sata|scif[ab]*|sdhi|thermal|tmu|tpu|usb(2|hs)?|vin|xhci)-[a-z0-9-]+$'
	'renesas,gp-evk' does not match '^renesas,(d|s)?bsc(3)?-(r8a73a4|r8a7740|sh73a0)$'
	'renesas,gp-evk' does not match '^renesas,em-(gio|sti|uart)$'
	'renesas,gp-evk' does not match '^renesas,fsi2-(r8a7740|sh73a0)$'
	'renesas,gp-evk' does not match '^renesas,hspi-r8a777[89]$'
	'renesas,gp-evk' does not match '^renesas,sysc-(r8a73a4|r8a7740|rmobile|sh73a0)$'
	'renesas,gp-evk' is not one of ['renesas,imr-lx4', 'renesas,mtu2-r7s72100']
	'renesas,gp-evk' is not one of ['renesas,smp-sram']
	'renesas,gp-evk' does not match '^(?!renesas,.+-.+).+$'
	from schema $id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: /: failed to match any schema with compatible: ['renesas,gp-evk', 'renesas,r9a09g057h44', 'renesas,r9a09g057']
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c00000: clocks: [[3, 1, 163], [3, 1, 165], [3, 1, 164], [3, 1, 166]] is too long
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c00000: clock-names:1: 'cd' was expected
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c00000: clock-names: ['core', 'clkh', 'cd', 'aclk'] is too long
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c10000: clocks: [[3, 1, 167], [3, 1, 169], [3, 1, 168], [3, 1, 170]] is too long
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c10000: clock-names:1: 'cd' was expected
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c10000: clock-names: ['core', 'clkh', 'cd', 'aclk'] is too long
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c20000: clocks: [[3, 1, 171], [3, 1, 173], [3, 1, 172], [3, 1, 174]] is too long
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c20000: clock-names:1: 'cd' was expected
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dtb: mmc@15c20000: clock-names: ['core', 'clkh', 'cd', 'aclk'] is too long
	from schema $id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#

Re: [PATCH v2 4/8] arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes

[claudiu beznea]

Hi, Prabhakar,

On 11.08.2024 23:49, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add RIIC0-RIIC8 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - New patch
> ---
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 198 +++++++++++++++++++++
>  1 file changed, 198 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> index 3d6c3a604ec9..c9e1e21b820d 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -141,6 +141,28 @@ ostm1: timer@11801000 {
>  			status = "disabled";
>  		};
>  
> +		i2c8: i2c@11c01000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "renesas,riic-r9a09g057";
> +			reg = <0 0x11c01000 0 0x400>;

According to [1] compatible and reg props are preferred to be at the
beginning of the node.

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n112

> +			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "tei", "ri", "ti", "spi", "sti",
> +					  "naki", "ali", "tmoi";
> +			clocks = <&cpg CPG_MOD 147>;
> +			clock-frequency = <100000>;
> +			resets = <&cpg 160>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +

[ ... ]

Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Aug 12, 2024 at 2:32 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Sunday, August 11, 2024 9:50 PM
> > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - New patch
> > > ---
> > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> > >  1 file changed, 44 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt0: watchdog@11c00400 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x11c00400 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 75>,
> > > +                              <&cpg CPG_MOD 76>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 117>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > >               ostm4: timer@12c00000 {
> > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > >                       reg = <0x0 0x12c00000 0x0 0x1000>;
> > > @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt2: watchdog@13000000 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x13000000 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 79>,
> > > +                              <&cpg CPG_MOD 80>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 119>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> >
> > I guess same group(all wdt together) arranged together?? Not sure.
> >
> I think Geert prefers it to be sorted based on unit address. So I'll
> let Geert make a decision on this (and the rest of the similar patches
> where nodes are sorted based on unit address and not grouped based on
> IP).

Sorted based on unit-address, but keep all nodes of the same type together.
I.e.:
    wdt0: watchdog@11c00400 { ... };
    wdt2: watchdog@13000000 { ... };
    wdt3: watchdog@13000400 { ... };
    wdt1: watchdog@14400000 { ... };

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

[Lad, Prabhakar]

Hi Geert,

On Mon, Aug 19, 2024 at 2:58 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Aug 12, 2024 at 2:32 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Sunday, August 11, 2024 9:50 PM
> > > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > - New patch
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> > > >  1 file changed, 44 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt0: watchdog@11c00400 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x11c00400 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 75>,
> > > > +                              <&cpg CPG_MOD 76>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 117>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > >               ostm4: timer@12c00000 {
> > > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > > >                       reg = <0x0 0x12c00000 0x0 0x1000>;
> > > > @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt2: watchdog@13000000 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x13000000 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 79>,
> > > > +                              <&cpg CPG_MOD 80>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 119>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > >
> > > I guess same group(all wdt together) arranged together?? Not sure.
> > >
> > I think Geert prefers it to be sorted based on unit address. So I'll
> > let Geert make a decision on this (and the rest of the similar patches
> > where nodes are sorted based on unit address and not grouped based on
> > IP).
>
> Sorted based on unit-address, but keep all nodes of the same type together.
> I.e.:
>     wdt0: watchdog@11c00400 { ... };
>     wdt2: watchdog@13000000 { ... };
>     wdt3: watchdog@13000400 { ... };
>     wdt1: watchdog@14400000 { ... };
>
Got you, I will update the patches with above sorting and send a v3.

Cheers,
Prabhakar

Re: [PATCH v2 4/8] arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes

[Lad, Prabhakar]

Hi Claudiu,

On Mon, Aug 19, 2024 at 9:13 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>
> Hi, Prabhakar,
>
> On 11.08.2024 23:49, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add RIIC0-RIIC8 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - New patch
> > ---
> >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 198 +++++++++++++++++++++
> >  1 file changed, 198 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > index 3d6c3a604ec9..c9e1e21b820d 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -141,6 +141,28 @@ ostm1: timer@11801000 {
> >                       status = "disabled";
> >               };
> >
> > +             i2c8: i2c@11c01000 {
> > +                     #address-cells = <1>;
> > +                     #size-cells = <0>;
> > +                     compatible = "renesas,riic-r9a09g057";
> > +                     reg = <0 0x11c01000 0 0x400>;
>
> According to [1] compatible and reg props are preferred to be at the
> beginning of the node.
>
Thanks I'll update the nodes according to [1].

> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n112
>

Cheers,
Prabhakar

> > +                     interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> > +                     interrupt-names = "tei", "ri", "ti", "spi", "sti",
> > +                                       "naki", "ali", "tmoi";
> > +                     clocks = <&cpg CPG_MOD 147>;
> > +                     clock-frequency = <100000>;
> > +                     resets = <&cpg 160>;
> > +                     power-domains = <&cpg>;
> > +                     status = "disabled";
> > +             };
> > +
>
> [ ... ]