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From: "tip-bot2 for Ahmed S. Darwish" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Ingo Molnar <mingo@kernel.org>,
	"Ahmed S. Darwish" <darwi@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2
Date: Tue, 25 Mar 2025 09:05:36 -0000	[thread overview]
Message-ID: <174289353695.14745.10612895286678737485.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20250324142042.29010-19-darwi@linutronix.de>

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     5e0c3c5e95f09236e5f7a73615bfa2666c58f182
Gitweb:        https://git.kernel.org/tip/5e0c3c5e95f09236e5f7a73615bfa2666c58f182
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Mon, 24 Mar 2025 15:20:39 +01:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Tue, 25 Mar 2025 09:53:47 +01:00

tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2

Update kcpuid's CSV file to version 2.2, as generated by x86-cpuid-db.

Per Ingo Molnar's feedback, it is desired to always use CPUID in its
capitalized form.  The v2.2 release fixed all instances of small case
"cpuid" at the project's XML database, and thus all of its generated
files.

Reported-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.2/CHANGELOG.rst
Link: https://lore.kernel.org/r/20250324142042.29010-19-darwi@linutronix.de

Closes: https://lkml.kernel.org/r/Z8bHK391zKE4gUEW@gmail.com
---
 tools/arch/x86/kcpuid/cpuid.csv | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index 0f9c112..9613e09 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: CC0-1.0
-# Generator: x86-cpuid-db v2.1
+# Generator: x86-cpuid-db v2.2
 
 #
 # Auto-generated file.
@@ -12,7 +12,7 @@
 # Leaf 0H
 # Maximum standard leaf number + CPU vendor string
 
-       0x0,         0,  eax,    31:0,    max_std_leaf           , Highest cpuid standard leaf supported
+       0x0,         0,  eax,    31:0,    max_std_leaf           , Highest standard CPUID leaf supported
        0x0,         0,  ebx,    31:0,    cpu_vendorid_0         , CPU vendor ID string bytes 0 - 3
        0x0,         0,  ecx,    31:0,    cpu_vendorid_2         , CPU vendor ID string bytes 8 - 11
        0x0,         0,  edx,    31:0,    cpu_vendorid_1         , CPU vendor ID string bytes 4 - 7
@@ -193,7 +193,7 @@
 # Leaf 7H
 # Extended CPU features enumeration
 
-       0x7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of cpuid 0x7 subleaves
+       0x7,         0,  eax,    31:0,    leaf7_n_subleaves      , Number of leaf 0x7 subleaves
        0x7,         0,  ebx,       0,    fsgsbase               , FSBASE/GSBASE read/write support
        0x7,         0,  ebx,       1,    tsc_adjust             , IA32_TSC_ADJUST MSR supported
        0x7,         0,  ebx,       2,    sgx                    , Intel SGX (Software Guard Extensions)
@@ -281,7 +281,7 @@
        0x7,         1,  eax,       5,    avx512_bf16            , AVX-512 bfloat16 instructions
        0x7,         1,  eax,       6,    lass                   , Linear address space separation
        0x7,         1,  eax,       7,    cmpccxadd              , CMPccXADD instructions
-       0x7,         1,  eax,       8,    arch_perfmon_ext       , ArchPerfmonExt: CPUID leaf 0x23 is supported
+       0x7,         1,  eax,       8,    arch_perfmon_ext       , ArchPerfmonExt: leaf 0x23 is supported
        0x7,         1,  eax,      10,    fzrm                   , Fast zero-length REP MOVSB
        0x7,         1,  eax,      11,    fsrs                   , Fast short REP STOSB
        0x7,         1,  eax,      12,    fsrc                   , Fast Short REP CMPSB/SCASB
@@ -319,7 +319,7 @@
        0xa,         0,  eax,     7:0,    pmu_version            , Performance monitoring unit version ID
        0xa,         0,  eax,    15:8,    pmu_n_gcounters        , Number of general PMU counters per logical CPU
        0xa,         0,  eax,   23:16,    pmu_gcounters_nbits    , Bitwidth of PMU general counters
-       0xa,         0,  eax,   31:24,    pmu_cpuid_ebx_bits     , Length of cpuid leaf 0xa EBX bit vector
+       0xa,         0,  eax,   31:24,    pmu_cpuid_ebx_bits     , Length of leaf 0xa EBX bit vector
        0xa,         0,  ebx,       0,    no_core_cycle_evt      , Core cycle event not available
        0xa,         0,  ebx,       1,    no_insn_retired_evt    , Instruction retired event not available
        0xa,         0,  ebx,       2,    no_refcycle_evt        , Reference cycles event not available
@@ -453,7 +453,7 @@
 # Leaf 14H
 # Intel Processor Trace enumeration
 
-      0x14,         0,  eax,    31:0,    pt_max_subleaf         , Max cpuid 0x14 subleaf
+      0x14,         0,  eax,    31:0,    pt_max_subleaf         , Maximum leaf 0x14 subleaf
       0x14,         0,  ebx,       0,    cr3_filtering          , IA32_RTIT_CR3_MATCH is accessible
       0x14,         0,  ebx,       1,    psb_cyc                , Configurable PSB and cycle-accurate mode
       0x14,         0,  ebx,       2,    ip_filtering           , IP/TraceStop filtering; Warm-reset PT MSRs preservation
@@ -490,7 +490,7 @@
 # Leaf 17H
 # Intel SoC vendor attributes enumeration
 
-      0x17,         0,  eax,    31:0,    soc_max_subleaf        , Max cpuid leaf 0x17 subleaf
+      0x17,         0,  eax,    31:0,    soc_max_subleaf        , Maximum leaf 0x17 subleaf
       0x17,         0,  ebx,    15:0,    soc_vendor_id          , SoC vendor ID
       0x17,         0,  ebx,      16,    is_vendor_scheme       , Assigned by industry enumeration scheme (not Intel)
       0x17,         0,  ecx,    31:0,    soc_proj_id            , SoC project ID, assigned by vendor
@@ -503,7 +503,7 @@
 # Leaf 18H
 # Intel determenestic address translation (TLB) parameters
 
-      0x18,      31:0,  eax,    31:0,    tlb_max_subleaf        , Max cpuid 0x18 subleaf
+      0x18,      31:0,  eax,    31:0,    tlb_max_subleaf        , Maximum leaf 0x18 subleaf
       0x18,      31:0,  ebx,       0,    tlb_4k_page            , TLB 4KB-page entries supported
       0x18,      31:0,  ebx,       1,    tlb_2m_page            , TLB 2MB-page entries supported
       0x18,      31:0,  ebx,       2,    tlb_4m_page            , TLB 4MB-page entries supported
@@ -634,7 +634,7 @@
 # Leaf 80000000H
 # Maximum extended leaf number + AMD/Transmeta CPU vendor string
 
-0x80000000,         0,  eax,    31:0,    max_ext_leaf           , Maximum extended cpuid leaf supported
+0x80000000,         0,  eax,    31:0,    max_ext_leaf           , Maximum extended CPUID leaf supported
 0x80000000,         0,  ebx,    31:0,    cpu_vendorid_0         , Vendor ID string bytes 0 - 3
 0x80000000,         0,  ecx,    31:0,    cpu_vendorid_2         , Vendor ID string bytes 8 - 11
 0x80000000,         0,  edx,    31:0,    cpu_vendorid_1         , Vendor ID string bytes 4 - 7
@@ -669,7 +669,7 @@
 0x80000001,         0,  ecx,      17,    tce                    , Translation cache extension
 0x80000001,         0,  ecx,      19,    nodeid_msr             , NodeId MSR (0xc001100c)
 0x80000001,         0,  ecx,      21,    tbm                    , Trailing bit manipulations
-0x80000001,         0,  ecx,      22,    topoext                , Topology Extensions (cpuid leaf 0x8000001d)
+0x80000001,         0,  ecx,      22,    topoext                , Topology Extensions (leaf 0x8000001d)
 0x80000001,         0,  ecx,      23,    perfctr_core           , Core performance counter extensions
 0x80000001,         0,  ecx,      24,    perfctr_nb             , NB/DF performance counter extensions
 0x80000001,         0,  ecx,      26,    bpext                  , Data access breakpoint extension

  reply	other threads:[~2025-03-25  9:05 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-24 14:20 [PATCH v3 00/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.3 Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 01/20] tools/x86/kcpuid: Fix error handling Ahmed S. Darwish
2025-03-25  8:55   ` Ingo Molnar
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 02/20] tools/x86/kcpuid: Exit the program on invalid parameters Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 03/20] tools/x86/kcpuid: Simplify usage() handling Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 04/20] tools/x86/kcpuid: Save CPUID output in an array Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 05/20] tools/x86/kcpuid: Print correct CPUID output register names Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 06/20] tools/x86/kcpuid: Remove unused local variable Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 07/20] tools/x86/kcpuid: Remove unused global variable Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 08/20] tools/x86/kcpuid: Set function return type to void Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] tools/x86/kcpuid: Set parse_line() " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 09/20] tools/x86/kcpuid: Use C99-style for loops Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 10/20] tools/x86/kcpuid: Use <cpuid.h> intrinsics Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 11/20] tools/x86/kcpuid: Refactor CPUID range handling for future expansion Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 12/20] tools/x86/kcpuid: Extend CPUID index mask macro Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 13/20] tools/x86/kcpuid: Consolidate index validity checks Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 14/20] tools/x86/kcpuid: Filter valid CPUID ranges Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 15/20] tools/x86/kcpuid: Define Transmeta and Centaur index ranges Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 16/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0 Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 17/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.1 Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 18/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2 Ahmed S. Darwish
2025-03-25  9:05   ` tip-bot2 for Ahmed S. Darwish [this message]
2025-03-24 14:20 ` [PATCH v3 19/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.3 Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 14:20 ` [PATCH v3 20/20] MAINTAINERS: Include kcpuid under X86 CPUID DATABASE Ahmed S. Darwish
2025-03-25  9:05   ` [tip: x86/cpu] MAINTAINERS: Include the entire kcpuid/ directory under the X86 CPUID DATABASE entry tip-bot2 for Ahmed S. Darwish

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