* [PATCH v2 0/8] Add RZ/G3E GPT support
@ 2025-09-09 9:12 Biju
2025-09-09 9:12 ` [PATCH v2 1/8] dt-bindings: pwm: Document " Biju
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E GPT support. It has multiple clocks and resets compared to
RZ/G2L. Also prescale field width and factor for calculating prescale
are different.
v1->v2:
* Created separate document for RZ/G3E GPT.
* Updated commit header and description for binding patch.
* Added waveform callback conversion to this series.
* Collected tag.
* Added link to hardware manual
* Updated limitation section in driver patch.
Biju Das (8):
dt-bindings: pwm: Document RZ/G3E GPT support
pwm: rzg2l-gpt: Implementation of the waveform callbacks
pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct
rzg2l_gpt_info
pwm: rzg2l-gpt: Add calculate_prescale() callback to struct
rzg2l_gpt_info
pwm: rzg2l-gpt: Add RZ/G3E support
arm64: dts: renesas: r9a09g047: Add GPT nodes
arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board
.../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 ++++++++++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +
drivers/pwm/pwm-rzg2l-gpt.c | 268 ++++++++++-----
4 files changed, 705 insertions(+), 83 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
base-commit: 65dd046ef55861190ecde44c6d9fcde54b9fb77d
prerequisite-patch-id: 994e29857383f8aa61bdc53df997f6e28f5cb723
prerequisite-patch-id: 81a4395c1935f9cc757743c5de646bf17a1bcfa0
prerequisite-patch-id: 34306f03faabbe6a0c238225e748b1d76726fd2c
prerequisite-patch-id: fd30b02c03eb26ef5c899a999964b4011e8c2e8e
prerequisite-patch-id: 93a5224b3caedf84145f925131c583f31332bdde
prerequisite-patch-id: 12f1505eeca8d5d136d8eac74573f6d2bdffa153
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/8] dt-bindings: pwm: Document RZ/G3E GPT support
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
@ 2025-09-09 9:12 ` Biju
2025-09-10 15:14 ` Rob Herring (Arm)
2025-09-09 9:12 ` [PATCH v2 2/8] pwm: rzg2l-gpt: Implementation of the waveform callbacks Biju
` (6 subsequent siblings)
7 siblings, 1 reply; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
SoC.
The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel
and GPT1: 8channels). The hardware supports simultaneous control of
all channels. PWM waveforms can be generated by controlling the
up-counter, downcounter, or up- and down-counter.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Created separate document for RZ/G3E GPT.
* Updated commit header and description.
---
.../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++
1 file changed, 323 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
new file mode 100644
index 000000000000..cb4ffab5f47f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
@@ -0,0 +1,323 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E General PWM Timer (GPT)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit
+ timer. It supports the following functions
+ * 32 bits x 16 channels.
+ * Up-counting or down-counting (saw waves) or up/down-counting
+ (triangle waves) for each counter.
+ * Clock sources independently selectable for each channel.
+ * Four I/O pins per channel.
+ * Two output compare/input capture registers per channel.
+ * For the two output compare/input capture registers of each channel,
+ four registers are provided as buffer registers and are capable of
+ operating as comparison registers when buffering is not in use.
+ * In output compare operation, buffer switching can be at crests or
+ troughs, enabling the generation of laterally asymmetric PWM waveforms.
+ * Registers for setting up frame cycles in each channel (with capability
+ for generating interrupts at overflow or underflow)
+ * Generation of dead times in PWM operation.
+ * Synchronous starting, stopping and clearing counters for arbitrary
+ channels.
+ * Count start, count stop, count clear, up-count, down-count, or input
+ capture operation in response to a maximum of 8 ELC events.
+ * Count start, count stop, count clear, up-count, down-count, or input
+ capture operation in response to the status of two input pins.
+ * Starting, clearing, stopping and up/down counters in response to a
+ maximum of four external triggers.
+ * Output pin disable function by detected short-circuits between output
+ pins.
+ * A/D converter start triggers can be generated.
+ * Compare match A to F event and overflow/underflow event can be output
+ to the ELC.
+ * Enables the noise filter for input capture.
+ * Logical operation between the channel output.
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r9a09g047-gpt # RZ/G3E
+
+ reg:
+ maxItems: 1
+
+ '#pwm-cells':
+ const: 3
+
+ interrupts:
+ items:
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.0
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.0
+ - description: A and B both high interrupt for channel GPT{0,1}.0
+ - description: A and B both low interrupt for channel GPT{0,1}.0
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.1
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.1
+ - description: A and B both high interrupt for channel GPT{0,1}.1
+ - description: A and B both low interrupt for channel GPT{0,1}.1
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.2
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.2
+ - description: A and B both high interrupt for channel GPT{0,1}.2
+ - description: A and B both low interrupt for channel GPT{0,1}.2
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.3
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.3
+ - description: A and B both high interrupt for channel GPT{0,1}.3
+ - description: A and B both low interrupt for channel GPT{0,1}.3
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.4
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.4
+ - description: A and B both high interrupt for channel GPT{0,1}.4
+ - description: A and B both low interrupt for channel GPT{0,1}.4
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.5
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.5
+ - description: A and B both high interrupt for channel GPT{0,1}.5
+ - description: A and B both low interrupt for channel GPT{0,1}.5
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.6
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.6
+ - description: A and B both high interrupt for channel GPT{0,1}.6
+ - description: A and B both low interrupt for channel GPT{0,1}.6
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.7
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.7
+ - description: A and B both high interrupt for channel GPT{0,1}.7
+ - description: A and B both low interrupt for channel GPT{0,1}.7
+
+ interrupt-names:
+ items:
+ - const: gtcia0
+ - const: gtcib0
+ - const: gtcic0
+ - const: gtcid0
+ - const: gtcie0
+ - const: gtcif0
+ - const: gtcih0
+ - const: gtcil0
+ - const: gtcia1
+ - const: gtcib1
+ - const: gtcic1
+ - const: gtcid1
+ - const: gtcie1
+ - const: gtcif1
+ - const: gtcih1
+ - const: gtcil1
+ - const: gtcia2
+ - const: gtcib2
+ - const: gtcic2
+ - const: gtcid2
+ - const: gtcie2
+ - const: gtcif2
+ - const: gtcih2
+ - const: gtcil2
+ - const: gtcia3
+ - const: gtcib3
+ - const: gtcic3
+ - const: gtcid3
+ - const: gtcie3
+ - const: gtcif3
+ - const: gtcih3
+ - const: gtcil3
+ - const: gtcia4
+ - const: gtcib4
+ - const: gtcic4
+ - const: gtcid4
+ - const: gtcie4
+ - const: gtcif4
+ - const: gtcih4
+ - const: gtcil4
+ - const: gtcia5
+ - const: gtcib5
+ - const: gtcic5
+ - const: gtcid5
+ - const: gtcie5
+ - const: gtcif5
+ - const: gtcih5
+ - const: gtcil5
+ - const: gtcia6
+ - const: gtcib6
+ - const: gtcic6
+ - const: gtcid6
+ - const: gtcie6
+ - const: gtcif6
+ - const: gtcih6
+ - const: gtcil6
+ - const: gtcia7
+ - const: gtcib7
+ - const: gtcic7
+ - const: gtcid7
+ - const: gtcie7
+ - const: gtcif7
+ - const: gtcih7
+ - const: gtcil7
+
+ clocks:
+ items:
+ - description: Core clock (PCLKD)
+ - description: Bus clock (PCLKA)
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: Reset for bus clock (PCLKA/PCLKD)
+ - description: Reset for core clock (PCLKD)
+
+ reset-names:
+ items:
+ - const: rst_p
+ - const: rst_s
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: pwm.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pwm@13010000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0x13010000 0x10000>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
+ clock-names = "core", "bus";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x59>, <&cpg 0x5a>;
+ reset-names = "rst_p", "rst_s";
+ #pwm-cells = <3>;
+ };
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/8] pwm: rzg2l-gpt: Implementation of the waveform callbacks
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
2025-09-09 9:12 ` [PATCH v2 1/8] dt-bindings: pwm: Document " Biju
@ 2025-09-09 9:12 ` Biju
2025-09-09 9:12 ` [PATCH v2 3/8] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Biju Das, linux-pwm, linux-kernel, Geert Uytterhoeven,
Prabhakar Mahadev Lad, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Convert the rzg2l-gpt driver to use the new callbacks for hardware
programming.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Dropped modifing hardware from .round_waveform_tohw() callback.
---
drivers/pwm/pwm-rzg2l-gpt.c | 175 +++++++++++++++++++++---------------
1 file changed, 102 insertions(+), 73 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 360c8bf3b190..f0a8531457ca 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -86,6 +86,13 @@ struct rzg2l_gpt_chip {
u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS];
};
+/* This represents a hardware configuration for one channel */
+struct rzg2l_gpt_waveform {
+ u32 gtpr;
+ u32 gtccr;
+ u8 prescale;
+};
+
static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
{
return pwmchip_get_drvdata(chip);
@@ -190,8 +197,10 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
/* Stop count, Output low on GTIOCx pin when counting stops */
rzg2l_gpt->channel_enable_count[ch]--;
- if (!rzg2l_gpt->channel_enable_count[ch])
+ if (!rzg2l_gpt->channel_enable_count[ch]) {
rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
+ rzg2l_gpt->period_ticks[ch] = 0;
+ }
/* Disable pin output */
rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), RZG2L_GTIOR_OxE(sub_ch), 0);
@@ -215,54 +224,37 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
}
-static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
- struct pwm_state *state)
-{
- struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
-
- state->enabled = rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm);
- if (state->enabled) {
- u32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
- u32 ch = RZG2L_GET_CH(pwm->hwpwm);
- u8 prescale;
- u32 val;
-
- val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
- prescale = FIELD_GET(RZG2L_GTCR_TPCS, val);
-
- val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
- state->period = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);
-
- val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
- state->duty_cycle = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);
- if (state->duty_cycle > state->period)
- state->duty_cycle = state->period;
- }
-
- state->polarity = PWM_POLARITY_NORMAL;
-
- return 0;
-}
-
static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
{
return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
U32_MAX);
}
-/* Caller holds the lock while calling rzg2l_gpt_config() */
-static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
- const struct pwm_state *state)
+static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const struct pwm_waveform *wf,
+ void *_wfhw)
+
{
struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
- u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
+ struct rzg2l_gpt_waveform *wfhw = _wfhw;
u8 ch = RZG2L_GET_CH(pwm->hwpwm);
u64 period_ticks, duty_ticks;
unsigned long pv, dc;
- u8 prescale;
+
+ guard(mutex)(&rzg2l_gpt->lock);
+ if (wf->period_length_ns == 0) {
+ *wfhw = (struct rzg2l_gpt_waveform){
+ .gtpr = 0,
+ .gtccr = 0,
+ .prescale = 0,
+ };
+
+ return 0;
+ }
/* Limit period/duty cycle to max value supported by the HW */
- period_ticks = mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, USEC_PER_SEC);
+ period_ticks = mul_u64_u64_div_u64(wf->period_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
if (period_ticks > RZG2L_MAX_TICKS)
period_ticks = RZG2L_MAX_TICKS;
/*
@@ -277,13 +269,14 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
period_ticks = rzg2l_gpt->period_ticks[ch];
}
- prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
- pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale);
-
- duty_ticks = mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz, USEC_PER_SEC);
+ wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
+ pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);
+ wfhw->gtpr = pv;
+ duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
if (duty_ticks > period_ticks)
duty_ticks = period_ticks;
- dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale);
+ dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);
+ wfhw->gtccr = dc;
/*
* GPT counter is shared by multiple channels, we cache the period ticks
@@ -292,6 +285,58 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
*/
rzg2l_gpt->period_ticks[ch] = period_ticks;
+ return 0;
+}
+
+static int rzg2l_gpt_round_waveform_fromhw(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const void *_wfhw,
+ struct pwm_waveform *wf)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
+ const struct rzg2l_gpt_waveform *wfhw = _wfhw;
+
+ wf->period_length_ns = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw->gtpr,
+ wfhw->prescale);
+ wf->duty_length_ns = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw->gtccr,
+ wfhw->prescale);
+ wf->duty_offset_ns = 0;
+
+ return 0;
+}
+
+static int rzg2l_gpt_read_waveform(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ void *_wfhw)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
+ struct rzg2l_gpt_waveform *wfhw = _wfhw;
+ u32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
+ u32 ch = RZG2L_GET_CH(pwm->hwpwm);
+ u32 gtcr;
+
+ if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm)) {
+ gtcr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
+ wfhw->prescale = FIELD_GET(RZG2L_GTCR_TPCS, gtcr);
+ wfhw->gtpr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
+ wfhw->gtccr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
+ if (wfhw->gtccr > wfhw->gtpr)
+ wfhw->gtccr = wfhw->gtpr;
+ }
+
+ return 0;
+}
+
+static int rzg2l_gpt_write_waveform(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const void *_wfhw)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
+ const struct rzg2l_gpt_waveform *wfhw = _wfhw;
+ u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
+ u8 ch = RZG2L_GET_CH(pwm->hwpwm);
+
+ guard(mutex)(&rzg2l_gpt->lock);
/*
* Counter must be stopped before modifying mode, prescaler, timer
* counter and buffer enable registers. These registers are shared
@@ -310,14 +355,14 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
/* Select count clock */
rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,
- FIELD_PREP(RZG2L_GTCR_TPCS, prescale));
+ FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale));
/* Set period */
- rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv);
+ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr);
}
/* Set duty cycle */
- rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc);
+ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), wfhw->gtccr);
if (rzg2l_gpt->channel_enable_count[ch] <= 1) {
/* Set initial value for counter */
@@ -326,44 +371,28 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
/* Set no buffer operation */
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0);
- /* Restart the counter after updating the registers */
- rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch),
- RZG2L_GTCR_CST, RZG2L_GTCR_CST);
- }
-
- return 0;
-}
-
-static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm,
- const struct pwm_state *state)
-{
- struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
- bool enabled = pwm->state.enabled;
- int ret;
-
- if (state->polarity != PWM_POLARITY_NORMAL)
- return -EINVAL;
-
- guard(mutex)(&rzg2l_gpt->lock);
- if (!state->enabled) {
- if (enabled)
- rzg2l_gpt_disable(rzg2l_gpt, pwm);
-
- return 0;
+ if (wfhw->gtpr)
+ /* Restart the counter after updating the registers */
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch),
+ RZG2L_GTCR_CST, RZG2L_GTCR_CST);
}
- ret = rzg2l_gpt_config(chip, pwm, state);
- if (!ret && !enabled)
+ if (wfhw->gtpr && !rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm))
rzg2l_gpt_enable(rzg2l_gpt, pwm);
+ else if (!wfhw->gtpr && rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm))
+ rzg2l_gpt_disable(rzg2l_gpt, pwm);
- return ret;
+ return 0;
}
static const struct pwm_ops rzg2l_gpt_ops = {
.request = rzg2l_gpt_request,
.free = rzg2l_gpt_free,
- .get_state = rzg2l_gpt_get_state,
- .apply = rzg2l_gpt_apply,
+ .sizeof_wfhw = sizeof(struct rzg2l_gpt_waveform),
+ .round_waveform_tohw = rzg2l_gpt_round_waveform_tohw,
+ .round_waveform_fromhw = rzg2l_gpt_round_waveform_fromhw,
+ .read_waveform = rzg2l_gpt_read_waveform,
+ .write_waveform = rzg2l_gpt_write_waveform,
};
static int rzg2l_gpt_probe(struct platform_device *pdev)
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/8] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
2025-09-09 9:12 ` [PATCH v2 1/8] dt-bindings: pwm: Document " Biju
2025-09-09 9:12 ` [PATCH v2 2/8] pwm: rzg2l-gpt: Implementation of the waveform callbacks Biju
@ 2025-09-09 9:12 ` Biju
2025-09-09 9:12 ` [PATCH v2 4/8] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3E GPT IP is similar to the one found on RZ/G2L GPT, but there are
some differences. The field width of prescalar on RZ/G3E is 4 whereas on
RZ/G2L it is 3. Add rzg2l_gpt_info variable to handle this differences.
The FIELD_PREP and FIELD_GET macro is giving compilation issue as the
parameters are not build time constants. So added Non-constant mask
variant of FIELD_GET() and FIELD_PREP().
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Collected tag.
---
drivers/pwm/pwm-rzg2l-gpt.c | 33 ++++++++++++++++++++++++++++-----
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index f0a8531457ca..bf989defa527 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -33,6 +33,19 @@
#include <linux/time.h>
#include <linux/units.h>
+/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
+#define field_get(_mask, _reg) \
+({\
+ typeof(_mask) (mask) = (_mask); \
+ (((_reg) & (mask)) >> (ffs(mask) - 1)); \
+})
+
+#define field_prep(_mask, _val) \
+({\
+ typeof(_mask) (mask) = (_mask); \
+ (((_val) << (ffs(mask) - 1)) & (mask)); \
+})
+
#define RZG2L_GET_CH(hwpwm) ((hwpwm) / 2)
#define RZG2L_GET_CH_OFFS(ch) (0x100 * (ch))
@@ -46,7 +59,6 @@
#define RZG2L_GTCR_CST BIT(0)
#define RZG2L_GTCR_MD GENMASK(18, 16)
-#define RZG2L_GTCR_TPCS GENMASK(26, 24)
#define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0)
@@ -77,9 +89,14 @@
#define RZG2L_MAX_SCALE_FACTOR 1024
#define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
+struct rzg2l_gpt_info {
+ u32 gtcr_tpcs_mask;
+};
+
struct rzg2l_gpt_chip {
void __iomem *mmio;
struct mutex lock; /* lock to protect shared channel resources */
+ const struct rzg2l_gpt_info *info;
unsigned long rate_khz;
u32 period_ticks[RZG2L_MAX_HW_CHANNELS];
u32 channel_request_count[RZG2L_MAX_HW_CHANNELS];
@@ -317,7 +334,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chip,
if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm)) {
gtcr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
- wfhw->prescale = FIELD_GET(RZG2L_GTCR_TPCS, gtcr);
+ wfhw->prescale = field_get(rzg2l_gpt->info->gtcr_tpcs_mask, gtcr);
wfhw->gtpr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
wfhw->gtccr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
if (wfhw->gtccr > wfhw->gtpr)
@@ -354,8 +371,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *chip,
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTING);
/* Select count clock */
- rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,
- FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale));
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs_mask,
+ field_prep(rzg2l_gpt->info->gtcr_tpcs_mask, wfhw->prescale));
/* Set period */
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr);
@@ -414,6 +431,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
if (IS_ERR(rzg2l_gpt->mmio))
return PTR_ERR(rzg2l_gpt->mmio);
+ rzg2l_gpt->info = of_device_get_match_data(dev);
+
rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
@@ -456,8 +475,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
return 0;
}
+static const struct rzg2l_gpt_info rzg2l_data = {
+ .gtcr_tpcs_mask = GENMASK(26, 24),
+};
+
static const struct of_device_id rzg2l_gpt_of_table[] = {
- { .compatible = "renesas,rzg2l-gpt", },
+ { .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 4/8] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
` (2 preceding siblings ...)
2025-09-09 9:12 ` [PATCH v2 3/8] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
@ 2025-09-09 9:12 ` Biju
2025-09-09 9:12 ` [PATCH v2 5/8] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.
Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info for
handling this difference.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Collected tag.
---
drivers/pwm/pwm-rzg2l-gpt.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index bf989defa527..74bb0cca4ab4 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -91,6 +91,7 @@
struct rzg2l_gpt_info {
u32 gtcr_tpcs_mask;
+ u8 prescale_pow_of_two_mult_factor;
};
struct rzg2l_gpt_chip {
@@ -226,6 +227,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
u32 val, u8 prescale)
{
+ const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
u64 tmp;
/*
@@ -235,15 +237,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
* < 2^32 * 2^10 * 2^20
* = 2^62
*/
- tmp = (u64)val << (2 * prescale);
+ tmp = (u64)val << (info->prescale_pow_of_two_mult_factor * prescale);
tmp *= USEC_PER_SEC;
return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
}
-static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
+static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,
+ u64 period_or_duty_cycle, u8 prescale)
{
- return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
+ return min_t(u64,
+ DIV_ROUND_DOWN_ULL(period_or_duty_cycle,
+ 1 << (info->prescale_pow_of_two_mult_factor * prescale)),
U32_MAX);
}
@@ -254,6 +259,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
{
struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
+ const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
struct rzg2l_gpt_waveform *wfhw = _wfhw;
u8 ch = RZG2L_GET_CH(pwm->hwpwm);
u64 period_ticks, duty_ticks;
@@ -287,12 +293,12 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
}
wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
- pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);
+ pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
wfhw->gtpr = pv;
duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
if (duty_ticks > period_ticks)
duty_ticks = period_ticks;
- dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);
+ dc = rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale);
wfhw->gtccr = dc;
/*
@@ -477,6 +483,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
static const struct rzg2l_gpt_info rzg2l_data = {
.gtcr_tpcs_mask = GENMASK(26, 24),
+ .prescale_pow_of_two_mult_factor = 2,
};
static const struct of_device_id rzg2l_gpt_of_table[] = {
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 5/8] pwm: rzg2l-gpt: Add calculate_prescale() callback to struct rzg2l_gpt_info
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
` (3 preceding siblings ...)
2025-09-09 9:12 ` [PATCH v2 4/8] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
@ 2025-09-09 9:12 ` Biju
2025-09-09 9:12 ` [PATCH v2 6/8] pwm: rzg2l-gpt: Add RZ/G3E support Biju
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L GPT the prescale factors are continuous power of 4 whereas on RZ/G3E
it is power of 2 but discontinuous. Add calculate_prescale() callback to
struct rzg2l_gpt_info for handling this difference.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Collected tag.
---
drivers/pwm/pwm-rzg2l-gpt.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 74bb0cca4ab4..b247a6c181d5 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -90,6 +90,7 @@
#define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
struct rzg2l_gpt_info {
+ u8 (*calculate_prescale)(u64 period);
u32 gtcr_tpcs_mask;
u8 prescale_pow_of_two_mult_factor;
};
@@ -138,8 +139,7 @@ static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 clr,
(rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set);
}
-static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt,
- u64 period_ticks)
+static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
{
u32 prescaled_period_ticks;
u8 prescale;
@@ -292,7 +292,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
period_ticks = rzg2l_gpt->period_ticks[ch];
}
- wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
+ wfhw->prescale = info->calculate_prescale(period_ticks);
pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
wfhw->gtpr = pv;
duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
@@ -482,6 +482,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
}
static const struct rzg2l_gpt_info rzg2l_data = {
+ .calculate_prescale = rzg2l_gpt_calculate_prescale,
.gtcr_tpcs_mask = GENMASK(26, 24),
.prescale_pow_of_two_mult_factor = 2,
};
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 6/8] pwm: rzg2l-gpt: Add RZ/G3E support
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
` (4 preceding siblings ...)
2025-09-09 9:12 ` [PATCH v2 5/8] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
@ 2025-09-09 9:12 ` Biju
2025-09-09 9:12 ` [PATCH v2 7/8] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
2025-09-09 9:12 ` [PATCH v2 8/8] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E GPT support. It has multiple clocks and resets compared to
RZ/G2L. Also prescale field width and factor for calculating prescale
are different.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Added link to hardware manual
* Updated limitation section
* Collected tag
---
drivers/pwm/pwm-rzg2l-gpt.c | 46 +++++++++++++++++++++++++++++++++++--
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index b247a6c181d5..57621a0bc4ac 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -6,15 +6,21 @@
*
* Hardware manual for this IP can be found here
* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
+ * https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardware
*
* Limitations:
* - Counter must be stopped before modifying Mode and Prescaler.
* - When PWM is disabled, the output is driven to inactive.
* - While the hardware supports both polarities, the driver (for now)
* only handles normal polarity.
- * - General PWM Timer (GPT) has 8 HW channels for PWM operations and
- * each HW channel have 2 IOs.
+ * - For RZ/G2L, the General PWM Timer (GPT) has 8 HW channels for PWM
+ operations and each HW channel have 2 IOs (GTIOCn{A, B}).
* - Each IO is modelled as an independent PWM channel.
+ * - For RZ/G3E, the General PWM Timer (GPT) has 16 HW channels for PWM
+ operations (GPT0: 8 channels, GPT1: 8 Channels) and each HW channel
+ have 4 IOs (GTIOCn{A,AN,B,BN}). The 2 extra IOs GTIOCnAN and GTIOCnBN
+ in RZ/G3E are anti-phase signals of GTIOCnA and GTIOCnB. The
+ anti-phase signals of RZ/G3E are not modelled as PWM channel.
* - When both channels are used, disabling the channel on one stops the
* other.
* - When both channels are used, the period of both IOs in the HW channel
@@ -153,6 +159,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
return prescale;
}
+static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks)
+{
+ u32 prescaled_period_ticks;
+ u8 prescale;
+
+ prescaled_period_ticks = period_ticks >> 32;
+ if (prescaled_period_ticks >= 64 && prescaled_period_ticks < 256) {
+ prescale = 6;
+ } else if (prescaled_period_ticks >= 256 && prescaled_period_ticks < 1024) {
+ prescale = 8;
+ } else if (prescaled_period_ticks >= 1024) {
+ prescale = 10;
+ } else {
+ prescale = fls(prescaled_period_ticks);
+ if (prescale > 1)
+ prescale -= 1;
+ }
+
+ return prescale;
+}
+
static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
@@ -443,6 +470,14 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
+ rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s");
+ if (IS_ERR(rstc))
+ return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n");
+
+ clk = devm_clk_get_optional_enabled(dev, "bus");
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n");
+
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
@@ -481,6 +516,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
return 0;
}
+static const struct rzg2l_gpt_info rzg3e_data = {
+ .calculate_prescale = rzg3e_gpt_calculate_prescale,
+ .gtcr_tpcs_mask = GENMASK(26, 23),
+ .prescale_pow_of_two_mult_factor = 1,
+};
+
static const struct rzg2l_gpt_info rzg2l_data = {
.calculate_prescale = rzg2l_gpt_calculate_prescale,
.gtcr_tpcs_mask = GENMASK(26, 24),
@@ -488,6 +529,7 @@ static const struct rzg2l_gpt_info rzg2l_data = {
};
static const struct of_device_id rzg2l_gpt_of_table[] = {
+ { .compatible = "renesas,r9a09g047-gpt", .data = &rzg3e_data },
{ .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
{ /* Sentinel */ }
};
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 7/8] arm64: dts: renesas: r9a09g047: Add GPT nodes
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
` (5 preceding siblings ...)
2025-09-09 9:12 ` [PATCH v2 6/8] pwm: rzg2l-gpt: Add RZ/G3E support Biju
@ 2025-09-09 9:12 ` Biju
2025-09-09 9:12 ` [PATCH v2 8/8] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
The RZ/G3E SoC has 2 GPT's. Add GPT nodes to RZ/G3E ("R9A09G047") SoC
DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e5b24e46d645..95d48a6fb7ed 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -587,6 +587,190 @@ channel5 {
};
};
+ gpt0: pwm@13010000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0 0x13010000 0 0x10000>;
+ #pwm-cells = <3>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
+ clock-names = "core", "bus";
+ resets = <&cpg 0x59>, <&cpg 0x5a>;
+ reset-names = "rst_p", "rst_s";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt1: pwm@13020000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0 0x13020000 0 0x10000>;
+ #pwm-cells = <3>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 610 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 618 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 626 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 642 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 658 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 627 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 659 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 628 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 636 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 652 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 660 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 613 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 621 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 629 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 637 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 661 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 614 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 622 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 630 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 646 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 662 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 631 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 647 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 663 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 632 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 656 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 609 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 617 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 625 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 633 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 665 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_MOD 0x32>, <&cpg CPG_MOD 0x32>;
+ clock-names = "core", "bus";
+ resets = <&cpg 0x5b>, <&cpg 0x5c>;
+ reset-names = "rst_p", "rst_s";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 8/8] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
` (6 preceding siblings ...)
2025-09-09 9:12 ` [PATCH v2 7/8] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
@ 2025-09-09 9:12 ` Biju
7 siblings, 0 replies; 10+ messages in thread
From: Biju @ 2025-09-09 9:12 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das, Tommaso Merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
The GTIOC4{A,B} IOs are available on the carrier board's PMOD1_6A
connector. Enable the GPT on the carrier board by adding the GPT pinmux
and node on the carrier board dtsi file.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Collected tags.
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..86df67e9230d 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -84,6 +84,14 @@ &can_transceiver1 {
};
#endif
+#if (!SW_LCD_EN) && (!SW_GPIO8_CAN0_STB)
+&gpt0 {
+ pinctrl-0 = <&gpt0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+#endif
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
@@ -125,6 +133,11 @@ can4_pins: can4 {
};
};
+ gpt0_pins: gpt0 {
+ pinmux = <RZG3E_PORT_PINMUX(5, 4, 10)>, /* GTIOC4A */
+ <RZG3E_PORT_PINMUX(5, 5, 10)>; /* GTIOC4B */
+ };
+
i2c0_pins: i2c0 {
pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */
<RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: pwm: Document RZ/G3E GPT support
2025-09-09 9:12 ` [PATCH v2 1/8] dt-bindings: pwm: Document " Biju
@ 2025-09-10 15:14 ` Rob Herring (Arm)
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring (Arm) @ 2025-09-10 15:14 UTC (permalink / raw)
To: Biju
Cc: linux-kernel, Biju Das, devicetree, Conor Dooley,
Uwe Kleine-König, Geert Uytterhoeven, Krzysztof Kozlowski,
Magnus Damm, Prabhakar Mahadev Lad, linux-pwm, linux-renesas-soc
On Tue, 09 Sep 2025 10:12:11 +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> SoC.
>
> The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel
> and GPT1: 8channels). The hardware supports simultaneous control of
> all channels. PWM waveforms can be generated by controlling the
> up-counter, downcounter, or up- and down-counter.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * Created separate document for RZ/G3E GPT.
> * Updated commit header and description.
> ---
> .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++
> 1 file changed, 323 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-09-10 15:14 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-09-09 9:12 [PATCH v2 0/8] Add RZ/G3E GPT support Biju
2025-09-09 9:12 ` [PATCH v2 1/8] dt-bindings: pwm: Document " Biju
2025-09-10 15:14 ` Rob Herring (Arm)
2025-09-09 9:12 ` [PATCH v2 2/8] pwm: rzg2l-gpt: Implementation of the waveform callbacks Biju
2025-09-09 9:12 ` [PATCH v2 3/8] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
2025-09-09 9:12 ` [PATCH v2 4/8] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
2025-09-09 9:12 ` [PATCH v2 5/8] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
2025-09-09 9:12 ` [PATCH v2 6/8] pwm: rzg2l-gpt: Add RZ/G3E support Biju
2025-09-09 9:12 ` [PATCH v2 7/8] arm64: dts: renesas: r9a09g047: Add GPT nodes Biju
2025-09-09 9:12 ` [PATCH v2 8/8] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Biju
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