[PATCH RFT 0/3] Fix always-enabling PCIE_RSCC clocks for multiple clk drivers

[PATCH RFT 0/3] Fix always-enabling PCIE_RSCC clocks for multiple clk drivers

[Luca Weiss]

I've noticed that the .clk_cbcrs list in multiple clock drivers enable
the GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK wrongly.

qcom_branch_set_clk_en() will be called on each entry which will set
BIT(0) to enable the clock, but this is wrong for these two clocks which
-- this is also why this is marked RFT -- at least for kaanapali
needs BIT(20) and BIT(21) set to enable them.

I don't know which downstream codename (in the vendor kernel) eliza and
hawi are so I just assumed the same BIT(20) and BIT(21) would be correct
there. Please verify this!

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Luca Weiss (3):
      clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks
      clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks
      clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks

 drivers/clk/qcom/gcc-eliza.c     | 6 ++++--
 drivers/clk/qcom/gcc-hawi.c      | 6 ++++--
 drivers/clk/qcom/gcc-kaanapali.c | 6 ++++--
 3 files changed, 12 insertions(+), 6 deletions(-)
---
base-commit: d56fa0b2bd2d9b2fddc10e8f5bdd42d56676935c
change-id: 20260807-various-pcie-clk-fix-6bafb619e7ab

Best regards,
--  
Luca Weiss <luca.weiss@fairphone.com>

[PATCH RFT 1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks

[Luca Weiss]

The critical_cbrcrs array will get qcom_branch_set_clk_en() called on
each entry which will set BIT(0) to enable the clock. This is however
wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set
respectively to enable them.

Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 drivers/clk/qcom/gcc-eliza.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
index 3e26c7a1e5b5..fe18942a59ac 100644
--- a/drivers/clk/qcom/gcc-eliza.c
+++ b/drivers/clk/qcom/gcc-eliza.c
@@ -3010,8 +3010,6 @@ static const u32 gcc_eliza_critical_cbcrs[] = {
 	0x26034, /* GCC_CAMERA_XO_CLK */
 	0x27004, /* GCC_DISP_AHB_CLK */
 	0x71004, /* GCC_GPU_CFG_AHB_CLK */
-	0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */
-	0x52010, /* GCC_PCIE_RSCC_XO_CLK */
 	0x32004, /* GCC_VIDEO_AHB_CLK */
 	0x32038, /* GCC_VIDEO_XO_CLK */
 };
@@ -3045,6 +3043,10 @@ static const struct regmap_config gcc_eliza_regmap_config = {
 
 static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
 {
+	/* Keep clocks always enabled */
+	regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_CFG_AHB_CLK */
+	regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* GCC_PCIE_RSCC_XO_CLK */
+
 	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);

-- 
2.55.0

[PATCH RFT 2/3] clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks

[Luca Weiss]

The critical_cbrcrs array will get qcom_branch_set_clk_en() called on
each entry which will set BIT(0) to enable the clock. This is however
wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set
respectively to enable them.

Fixes: 67121dad6cba ("clk: qcom: Add support for global clock controller on Hawi")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 drivers/clk/qcom/gcc-hawi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-hawi.c b/drivers/clk/qcom/gcc-hawi.c
index 6fb5a3db9586..f1b95753c3a3 100644
--- a/drivers/clk/qcom/gcc-hawi.c
+++ b/drivers/clk/qcom/gcc-hawi.c
@@ -3692,8 +3692,6 @@ static const u32 gcc_hawi_critical_cbcrs[] = {
 	0x67084, /* GCC_PCIE_1_RSC_CORE_CLK */
 	0x43014, /* GCC_PCIE_LINK_XO_CLK */
 	0x6b088, /* GCC_PCIE_RSC_CORE_CLK */
-	0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */
-	0x52010, /* GCC_PCIE_RSCC_XO_CLK */
 	0x32004, /* GCC_VIDEO_AHB_CLK */
 	0x32028, /* GCC_VIDEO_XO_CLK */
 };
@@ -3763,6 +3761,10 @@ static const struct regmap_config gcc_hawi_regmap_config = {
 
 static void clk_hawi_regs_configure(struct device *dev, struct regmap *regmap)
 {
+	/* Keep clocks always enabled */
+	regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_CFG_AHB_CLK */
+	regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* GCC_PCIE_RSCC_XO_CLK */
+
 	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
 }

-- 
2.55.0

[PATCH RFT 3/3] clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks

[Luca Weiss]

The critical_cbrcrs array will get qcom_branch_set_clk_en() called on
each entry which will set BIT(0) to enable the clock. This is however
wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set
respectively to enable them.

Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 drivers/clk/qcom/gcc-kaanapali.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanapali.c
index 842c1a70c691..5bcbcd178657 100644
--- a/drivers/clk/qcom/gcc-kaanapali.c
+++ b/drivers/clk/qcom/gcc-kaanapali.c
@@ -3464,8 +3464,6 @@ static const u32 gcc_kaanapali_critical_cbcrs[] = {
 	0x9f004, /* GCC_EVA_AHB_CLK */
 	0x9f024, /* GCC_EVA_XO_CLK */
 	0x71004, /* GCC_GPU_CFG_AHB_CLK */
-	0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */
-	0x52010, /* GCC_PCIE_RSCC_XO_CLK */
 	0x32004, /* GCC_VIDEO_AHB_CLK */
 	0x32040, /* GCC_VIDEO_XO_CLK */
 };
@@ -3480,6 +3478,10 @@ static const struct regmap_config gcc_kaanapali_regmap_config = {
 
 static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regmap)
 {
+	/* Keep clocks always enabled */
+	regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_CFG_AHB_CLK */
+	regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* GCC_PCIE_RSCC_XO_CLK */
+
 	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
 }

-- 
2.55.0

Re: [PATCH RFT 1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks

[Abel Vesa]

On 26-08-07 09:46:04, Luca Weiss wrote:
> The critical_cbrcrs array will get qcom_branch_set_clk_en() called on
> each entry which will set BIT(0) to enable the clock. This is however
> wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set
> respectively to enable them.
> 
> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>

Tested on CQS EVK, which does have PCIe endpoints.

Tested-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH RFT 0/3] Fix always-enabling PCIE_RSCC clocks for multiple clk drivers

[Bjorn Andersson]

On Fri, 07 Aug 2026 09:46:03 +0200, Luca Weiss wrote:
> I've noticed that the .clk_cbcrs list in multiple clock drivers enable
> the GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK wrongly.
> 
> qcom_branch_set_clk_en() will be called on each entry which will set
> BIT(0) to enable the clock, but this is wrong for these two clocks which
> -- this is also why this is marked RFT -- at least for kaanapali
> needs BIT(20) and BIT(21) set to enable them.
> 
> [...]

Applied, thanks!

[1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks
      commit: 34e0ef622cd41eb5ee77d6aae79276c12de7c20f
[2/3] clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks
      commit: c83e1427064e6fe95604b469f4c670e1839f409a
[3/3] clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks
      commit: 7f6869e53f73c4ca0e622a6a1b5ac2598fee5931

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH RFT 0/3] Fix always-enabling PCIE_RSCC clocks for multiple clk drivers

[Bjorn Andersson]

On Fri, 07 Aug 2026 09:46:03 +0200, Luca Weiss wrote:
> I've noticed that the .clk_cbcrs list in multiple clock drivers enable
> the GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK wrongly.
> 
> qcom_branch_set_clk_en() will be called on each entry which will set
> BIT(0) to enable the clock, but this is wrong for these two clocks which
> -- this is also why this is marked RFT -- at least for kaanapali
> needs BIT(20) and BIT(21) set to enable them.
> 
> [...]

Applied, thanks!

[1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks
      commit: 5ffd02d16f4e2f0566b8f31d5610538987e1944c
[2/3] clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks
      commit: 62bbf7ed9ad97c17377377aae50b7ea7feb9464e
[3/3] clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks
      commit: 0bfb542fc3368371cefb4cf45ef21c3ba2d37c3f

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>