Re: [PATCH v2 3/4] arm64: dts: qcom: ipq5424: add spi0 node

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 20.12.2024 8:25 AM, Manikanta Mylavarapu wrote:
> 
> 
> On 12/20/2024 2:06 AM, Konrad Dybcio wrote:
>> On 17.12.2024 10:13 AM, Manikanta Mylavarapu wrote:
>>> Add SPI0 node for IPQ5424 SoC.
>>>
>>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>>> ---
>>> Changes in V2:
>>> 	- No change
>>>
>>>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++
>>>  1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> index 5e219f900412..b4d736cd8610 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> @@ -201,6 +201,17 @@ uart1: serial@1a84000 {
>>>  				clock-names = "se";
>>>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>>>  			};
>>> +
>>> +			spi0: spi@1a90000 {
>>> +				compatible = "qcom,geni-spi";
>>> +				reg = <0 0x01a90000 0 0x4000>;
>>> +				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
>>
>> This register base suggests SPI4 for both the name and clock
>>
> 
> Hi Konrad,
> 
> Thank you for reviewing the patch.
> 
> The IPQ5424 doesn't have SPI4, and according to the Qualcomm IPQ5424 register catalog,
> the register base maps to SPI0.

I'm looking at that register catalog and what you added here is
called SE4

> 
>> The existing UART1 similarly should be UART0
> 
> I didn't understand your comment. UART0 not yet posted.
> In IPQ5424, UART1 is the main UART used for console
> and UART0 is HS-UART used for some debugging purpose.

Here it's my mistake, 0x01a84000 is SE1 indeed

Konrad