[PATCH v2 0/4] Add SPI0 support for IPQ5424

[PATCH v2 0/4] Add SPI0 support for IPQ5424

[Manikanta Mylavarapu]

Add an SPI0 node to the IPQ5424 device tree and update the relevant
bindings, GPIO pin mappings accordingly.

Changes in V2:
	- Fixed all review comments from Konrad Dybico, Krzysztof
	  Kozlowski
	- Detailed change logs are added to the respective patches 

V1 can be found at:
https://lore.kernel.org/linux-arm-msm/20241122124505.1688436-1-quic_mmanikan@quicinc.com/

Manikanta Mylavarapu (4):
  dt-bindings: pinctrl: qcom: update spi0 function
  pinctrl: qcom: ipq5424: split spi0 pin group
  arm64: dts: qcom: ipq5424: add spi0 node
  arm64: dts: qcom: ipq5424: configure spi0 node for rdp466

 .../bindings/pinctrl/qcom,ipq5424-tlmm.yaml   |  4 +-
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts   | 43 +++++++++++++++++++
 arch/arm64/boot/dts/qcom/ipq5424.dtsi         | 11 +++++
 drivers/pinctrl/qcom/pinctrl-ipq5424.c        | 34 +++++++++++----
 4 files changed, 82 insertions(+), 10 deletions(-)


base-commit: e25c8d66f6786300b680866c0e0139981273feba
-- 
2.34.1

[PATCH v2 1/4] dt-bindings: pinctrl: qcom: update spi0 function

[Manikanta Mylavarapu]

The GPIO configuration differs for the spi0 clk, cs, miso, mosi pins.
Therefore, split the spi0 pin group and document each pin function.

Fixes: b88752d3133b ("dt-bindings: pinctrl: qcom: add IPQ5424 pinctrl")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
Changes in V2:
	- Pick up A-b tag
	- Add Fixes tag

 .../devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml        | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml
index 5e64a232fc7a..df284d3645c1 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml
@@ -79,8 +79,8 @@ $defs:
                 qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
                 qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
                 qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
-                sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1,
-                wci_txd, wci_rxd, wsi_clk, wsi_data ]
+                sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10,
+                spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ]
 
     required:
       - pins
-- 
2.34.1

[PATCH v2 2/4] pinctrl: qcom: ipq5424: split spi0 pin group

[Manikanta Mylavarapu]

The GPIO configuration differs for the spi0 clk, cs, miso, mosi pins.
Therefore, split the spi0 pin group and assign function to each pin
as per the specification.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
Changes in V2:
	- No change

 drivers/pinctrl/qcom/pinctrl-ipq5424.c | 34 ++++++++++++++++++++------
 1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c
index 796299cd2e4e..0d610b076da3 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq5424.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c
@@ -233,7 +233,10 @@ enum ipq5424_functions {
 	msm_mux_sdc_clk,
 	msm_mux_sdc_cmd,
 	msm_mux_sdc_data,
-	msm_mux_spi0,
+	msm_mux_spi0_clk,
+	msm_mux_spi0_cs,
+	msm_mux_spi0_miso,
+	msm_mux_spi0_mosi,
 	msm_mux_spi1,
 	msm_mux_spi10,
 	msm_mux_spi11,
@@ -297,8 +300,8 @@ static const char * const qspi_clk_groups[] = {
 	"gpio5",
 };
 
-static const char * const spi0_groups[] = {
-	"gpio6", "gpio7", "gpio8", "gpio9",
+static const char * const spi0_clk_groups[] = {
+	"gpio6",
 };
 
 static const char * const pwm1_groups[] = {
@@ -315,14 +318,26 @@ static const char * const qdss_tracedata_a_groups[] = {
 	"gpio38", "gpio39",
 };
 
+static const char * const spi0_cs_groups[] = {
+	"gpio7",
+};
+
 static const char * const cri_trng1_groups[] = {
 	"gpio7",
 };
 
+static const char * const spi0_miso_groups[] = {
+	"gpio8",
+};
+
 static const char * const cri_trng2_groups[] = {
 	"gpio8",
 };
 
+static const char * const spi0_mosi_groups[] = {
+	"gpio9",
+};
+
 static const char * const cri_trng3_groups[] = {
 	"gpio9",
 };
@@ -680,7 +695,10 @@ static const struct pinfunction ipq5424_functions[] = {
 	MSM_PIN_FUNCTION(sdc_clk),
 	MSM_PIN_FUNCTION(sdc_cmd),
 	MSM_PIN_FUNCTION(sdc_data),
-	MSM_PIN_FUNCTION(spi0),
+	MSM_PIN_FUNCTION(spi0_clk),
+	MSM_PIN_FUNCTION(spi0_cs),
+	MSM_PIN_FUNCTION(spi0_miso),
+	MSM_PIN_FUNCTION(spi0_mosi),
 	MSM_PIN_FUNCTION(spi1),
 	MSM_PIN_FUNCTION(spi10),
 	MSM_PIN_FUNCTION(spi11),
@@ -700,10 +718,10 @@ static const struct msm_pingroup ipq5424_groups[] = {
 	PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
 	PINGROUP(4, sdc_cmd, qspi_cs, _, _, _, _, _, _, _),
 	PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
-	PINGROUP(6, spi0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
-	PINGROUP(7, spi0, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _),
-	PINGROUP(8, spi0, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _),
-	PINGROUP(9, spi0, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _),
+	PINGROUP(6, spi0_clk, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
+	PINGROUP(7, spi0_cs, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _),
+	PINGROUP(8, spi0_miso, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _),
+	PINGROUP(9, spi0_mosi, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _),
 	PINGROUP(10, uart0, pwm0, spi11, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _),
 	PINGROUP(11, uart0, pwm0, spi1, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _),
 	PINGROUP(12, uart0, pwm0, spi11, _, prng_rosc0, qdss_tracedata_a, _, _, _),
-- 
2.34.1

[PATCH v2 3/4] arm64: dts: qcom: ipq5424: add spi0 node

[Manikanta Mylavarapu]

Add SPI0 node for IPQ5424 SoC.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
Changes in V2:
	- No change

 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 5e219f900412..b4d736cd8610 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -201,6 +201,17 @@ uart1: serial@1a84000 {
 				clock-names = "se";
 				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 			};
+
+			spi0: spi@1a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x01a90000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		sdhc: mmc@7804000 {
-- 
2.34.1

[PATCH v2 4/4] arm64: dts: qcom: ipq5424: configure spi0 node for rdp466

[Manikanta Mylavarapu]

Enable the SPI0 node and configure the associated gpio pins.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
Changes in V2:
	- Updated the hierarchy of spi0 node.
	- Removed the outer qupv3 node and
	  moved spi0 node to top level.

 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 43 +++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index d4d31026a026..60cfa8708eb4 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -23,6 +23,36 @@ &sleep_clk {
 };
 
 &tlmm {
+	spi0_default_state: spi0-default-state {
+		clk-pins {
+			pins = "gpio6";
+			function = "spi0_clk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		cs-pins {
+			pins = "gpio7";
+			function = "spi0_cs";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		miso-pins {
+			pins = "gpio8";
+			function = "spi0_miso";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mosi-pins {
+			pins = "gpio9";
+			function = "spi0_mosi";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
 	sdc_default_state: sdc-default-state {
 		clk-pins {
 			pins = "gpio5";
@@ -57,3 +87,16 @@ &xo_board {
 	clock-frequency = <24000000>;
 };
 
+&spi0 {
+	pinctrl-0 = <&spi0_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
-- 
2.34.1

Re: [PATCH v2 0/4] Add SPI0 support for IPQ5424

[Linus Walleij]

On Tue, Dec 17, 2024 at 10:13 AM Manikanta Mylavarapu
<quic_mmanikan@quicinc.com> wrote:

> Add an SPI0 node to the IPQ5424 device tree and update the relevant
> bindings, GPIO pin mappings accordingly.
(...)
>   dt-bindings: pinctrl: qcom: update spi0 function
>   pinctrl: qcom: ipq5424: split spi0 pin group

These two applied to the pin control tree!

>   arm64: dts: qcom: ipq5424: add spi0 node
>   arm64: dts: qcom: ipq5424: configure spi0 node for rdp466

Please funnel these through the SoC tree!

Yours,
Linus Walleij

Re: [PATCH v2 3/4] arm64: dts: qcom: ipq5424: add spi0 node

[Konrad Dybcio]

On 17.12.2024 10:13 AM, Manikanta Mylavarapu wrote:
> Add SPI0 node for IPQ5424 SoC.
> 
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> ---
> Changes in V2:
> 	- No change
> 
>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 5e219f900412..b4d736cd8610 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -201,6 +201,17 @@ uart1: serial@1a84000 {
>  				clock-names = "se";
>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> +
> +			spi0: spi@1a90000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0 0x01a90000 0 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;

This register base suggests SPI4 for both the name and clock

The existing UART1 similarly should be UART0

Konrad

Re: [PATCH v2 3/4] arm64: dts: qcom: ipq5424: add spi0 node

[Manikanta Mylavarapu]

On 12/20/2024 2:06 AM, Konrad Dybcio wrote:
> On 17.12.2024 10:13 AM, Manikanta Mylavarapu wrote:
>> Add SPI0 node for IPQ5424 SoC.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>> ---
>> Changes in V2:
>> 	- No change
>>
>>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 5e219f900412..b4d736cd8610 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -201,6 +201,17 @@ uart1: serial@1a84000 {
>>  				clock-names = "se";
>>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>>  			};
>> +
>> +			spi0: spi@1a90000 {
>> +				compatible = "qcom,geni-spi";
>> +				reg = <0 0x01a90000 0 0x4000>;
>> +				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
> 
> This register base suggests SPI4 for both the name and clock
> 

Hi Konrad,

Thank you for reviewing the patch.

The IPQ5424 doesn't have SPI4, and according to the Qualcomm IPQ5424 register catalog,
the register base maps to SPI0.

> The existing UART1 similarly should be UART0

I didn't understand your comment. UART0 not yet posted.
In IPQ5424, UART1 is the main UART used for console
and UART0 is HS-UART used for some debugging purpose.

Thanks & Regards,
Manikanta.

Re: [PATCH v2 3/4] arm64: dts: qcom: ipq5424: add spi0 node

[Konrad Dybcio]

On 20.12.2024 8:25 AM, Manikanta Mylavarapu wrote:
> 
> 
> On 12/20/2024 2:06 AM, Konrad Dybcio wrote:
>> On 17.12.2024 10:13 AM, Manikanta Mylavarapu wrote:
>>> Add SPI0 node for IPQ5424 SoC.
>>>
>>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>>> ---
>>> Changes in V2:
>>> 	- No change
>>>
>>>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++
>>>  1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> index 5e219f900412..b4d736cd8610 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>> @@ -201,6 +201,17 @@ uart1: serial@1a84000 {
>>>  				clock-names = "se";
>>>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>>>  			};
>>> +
>>> +			spi0: spi@1a90000 {
>>> +				compatible = "qcom,geni-spi";
>>> +				reg = <0 0x01a90000 0 0x4000>;
>>> +				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
>>
>> This register base suggests SPI4 for both the name and clock
>>
> 
> Hi Konrad,
> 
> Thank you for reviewing the patch.
> 
> The IPQ5424 doesn't have SPI4, and according to the Qualcomm IPQ5424 register catalog,
> the register base maps to SPI0.

I'm looking at that register catalog and what you added here is
called SE4

> 
>> The existing UART1 similarly should be UART0
> 
> I didn't understand your comment. UART0 not yet posted.
> In IPQ5424, UART1 is the main UART used for console
> and UART0 is HS-UART used for some debugging purpose.

Here it's my mistake, 0x01a84000 is SE1 indeed

Konrad

Re: [PATCH v2 3/4] arm64: dts: qcom: ipq5424: add spi0 node

[Manikanta Mylavarapu]

On 12/20/2024 3:15 PM, Konrad Dybcio wrote:
> On 20.12.2024 8:25 AM, Manikanta Mylavarapu wrote:
>>
>>
>> On 12/20/2024 2:06 AM, Konrad Dybcio wrote:
>>> On 17.12.2024 10:13 AM, Manikanta Mylavarapu wrote:
>>>> Add SPI0 node for IPQ5424 SoC.
>>>>
>>>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>>>> ---
>>>> Changes in V2:
>>>> 	- No change
>>>>
>>>>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++
>>>>  1 file changed, 11 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>>> index 5e219f900412..b4d736cd8610 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>>>> @@ -201,6 +201,17 @@ uart1: serial@1a84000 {
>>>>  				clock-names = "se";
>>>>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>>>>  			};
>>>> +
>>>> +			spi0: spi@1a90000 {
>>>> +				compatible = "qcom,geni-spi";
>>>> +				reg = <0 0x01a90000 0 0x4000>;
>>>> +				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
>>>
>>> This register base suggests SPI4 for both the name and clock
>>>
>>
>> Hi Konrad,
>>
>> Thank you for reviewing the patch.
>>
>> The IPQ5424 doesn't have SPI4, and according to the Qualcomm IPQ5424 register catalog,
>> the register base maps to SPI0.
> 
> I'm looking at that register catalog and what you added here is
> called SE4
> 

I understand your point and will rename it to SPI4.

Thanks & Regards,
Manikanta.

>>
>>> The existing UART1 similarly should be UART0
>>
>> I didn't understand your comment. UART0 not yet posted.
>> In IPQ5424, UART1 is the main UART used for console
>> and UART0 is HS-UART used for some debugging purpose.
> 
> Here it's my mistake, 0x01a84000 is SE1 indeed
> 
> Konrad