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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
	dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
	Alexander Koskovich <akoskovich@pm.me>,
	Jie Zhang <jie.zhang@oss.qualcomm.com>,
	Akhil P Oommen <akhilpo@oss.qualcomm.com>,
	Bhaskar Reddy Valluru <bvalluru@qti.qualcomm.com>,
	Sean Paul <sean@poorly.run>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 13/14] drm/msm/a8xx: Switch to generated protect regs
Date: Thu, 22 Oct 2026 10:27:03 +0200	[thread overview]
Message-ID: <1c8f4222-e7e3-4b10-8826-60de6dd89a61@oss.qualcomm.com> (raw)
In-Reply-To: <20261021204244.67160-14-robin.clark@oss.qualcomm.com>

On 10/21/26 10:41 PM, Rob Clark wrote:
> These also fix some perfcntr SEL regs which were mistakenly blocked
> since we previously just copied the protect tables from downstream kgsl
> (and only sometimes remembered to fix these).
> 
> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
> ---

LLM summary in case anyone is interested:

- Almost nothing carries over unchanged. Only 22–34 entries per GPU match exactly, out of 47–64 in each table.
- The generated tables use finer-grained ranges. For example, NORDWR 0x8600, 0x1ff becomes several smaller ranges (0x8600/0xf, 0x8700/0xf, 0x8740/0xbf, and so on).
- Several ranges that were RDONLY before are now NORDWR, or the other way round, and some change length. Some ranges appear only in the new tables, such as 0xd200/0x3ff and 0x20000–0x27810 on maili.
- The generated tables don't reproduce some old ranges exactly. 0xfc00/0x1fff and 0x3cc6/0x1fff, for example, are not in the new tables. I didn't check whether the new tables still protect that address space.
- count_max goes from 15 to 64 for x285, a840 and a850. The old 15 was already below the 47–57 entries those tables held. Patch 13 also adds BUILD_BUG_ON checks for all six protect tables. Before, only a810 and a830 were checked, so the old mismatch went unnoticed.

Also one robo-worry:

Unexpected: on hawi, GRAS_PERFCTR_TSEFE_SEL at 0x8610 is still
blocked, because the new NORDWR 0x8600, 0x10f entry covers it.

Konrad

  reply	other threads:[~2026-10-22  8:27 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-21 20:41 [PATCH v2 00/14] drm/msm/a8xx: GPU state capture support Rob Clark
2026-10-21 20:41 ` [PATCH v2 01/14] drm/msm: Import adreno_snapshot.h Rob Clark
2026-10-21 20:41 ` [PATCH v2 02/14] drm/msm/a8xx: Export aperture helpers Rob Clark
2026-10-21 20:41 ` [PATCH v2 03/14] drm/msm/a8xx: Add a8xx_aperture_acquire_raw() Rob Clark
2026-10-21 20:41 ` [PATCH v2 04/14] drm/msm/a8xx: Export slice helper Rob Clark
2026-10-21 20:41 ` [PATCH v2 05/14] drm/msm/a8xx: Add missing a850 ifpc reglist entries Rob Clark
2026-10-22  7:19   ` Konrad Dybcio
2026-10-21 20:41 ` [PATCH v2 06/14] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Rob Clark
2026-10-21 20:41 ` [PATCH v2 07/14] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list Rob Clark
2026-10-21 20:41 ` [PATCH v2 08/14] drm/msm/adreno: Fix PROTECT span length Rob Clark
2026-10-21 20:41 ` [PATCH v2 09/14] drm/msm/adreno: add temporary __maybe_unused Rob Clark
2026-10-21 20:41 ` [PATCH v2 10/14] drm/msm/a8xx: Import generated headers Rob Clark
2026-10-21 20:41 ` [PATCH v2 11/14] drm/msm/a8xx: devcoredump state capture support Rob Clark
2026-10-21 20:41 ` [PATCH v2 12/14] drm/msm/a8xx: Switch to generated nonctx regs Rob Clark
2026-10-22  8:03   ` Konrad Dybcio
2026-10-21 20:41 ` [PATCH v2 13/14] drm/msm/a8xx: Switch to generated protect regs Rob Clark
2026-10-22  8:27   ` Konrad Dybcio [this message]
2026-10-21 20:41 ` [PATCH v2 14/14] drm/msm/adreno: Remove temporary __maybe_unused Rob Clark

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