From: Can Guo <can.guo@oss.qualcomm.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: bvanassche@acm.org, beanhuo@micron.com, peter.wang@mediatek.com,
martin.petersen@oracle.com, linux-scsi@vger.kernel.org,
Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>,
Zhaoming Luo <zhml@posteo.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] dt-bindings: ufs: Document static TX Equalization settings properties
Date: Wed, 27 May 2026 17:24:51 +0800 [thread overview]
Message-ID: <1cd587f0-d571-4bd8-a8c0-97248e732cec@oss.qualcomm.com> (raw)
In-Reply-To: <qrqggwpuigevauuzjcvggcmbzkphutemlpsvuymy7qn5yblnsd@djbgzgyeekre>
On 5/27/2026 5:15 PM, Manivannan Sadhasivam wrote:
> On Wed, May 27, 2026 at 04:51:04PM +0800, Can Guo wrote:
>> Hi Mani,
>>
>> On 5/23/2026 10:14 PM, Manivannan Sadhasivam wrote:
>>> On Sat, May 23, 2026 at 06:47:10AM -0700, Can Guo wrote:
>>>> UFS v5.0/UFSHCI v5.0 add HS-G6 support (46.6 Gbps/lane) via UniPro v3.0
>>>> and M-PHY v6.0. In these specs, TX Equalization is defined for all High
>>>> Speed Gears (not only HS-G6) to compensate channel loss and improve signal
>>>> integrity at high speed operation.
>>>>
>>>> For HS-G6, M-PHY uses PAM4 1b1b line coding, Pre-Coding may also be
>>>> required depending on channel characteristics.
>>>>
>>>> Add vendor-neutral DT patternProperties:
>>>> txeq-settings-g[1-6]
>>>>
>>>> Each property is a uint32 array of per-lane tuples:
>>>> (PreShoot, DeEmphasis, PrecodeEn)
>>>>
>>> I don't think combining all EQ settings (PreShoot, DeEmphasis, PrecodeEn) in a
>>> single property as opaque tuples is the right approach. These are three
>>> semantically distinct parameters with independent value ranges. So packing
>>> them into a uint32 array makes validation impossible in the schema.
>>>
>>> AFACIS, PrecodeEn is applicable only to HS-G6 (PAM4), but the proposed
>>> patternProperties forces it into G1-G5 tuples as well, which is semantically
>>> wrong.
>> Point taken for the PrecodeEn.
>>> PCIe binding defines one property per data rate for EQ presets:
>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml#L193
>>>
>>> Similarly, UFS should define one property per gear per (like, txeq-preshoot-g6,
>>> txeq-deemphasis-g6, txeq-precode-enable-g6,...) rather than clubbing everything
>>> into opaque tuples.
>> Thanks for the suggestion. I will go with below approach:
>>
>> txeq-preshoot-g6 = <Host Lane 0 PreShoot, Device Lane 0 PreShoot, Host Lane
>> 1 PreShoot, Device Lane 1 PreShoot>;
>> txeq-deemphasis-g6 = <Host Lane 0 DeEmphasis, Device Lane 0 DeEmphasis, Host
>> Lane 1 DeEmphasis, Device Lane 1 DeEmphasis>;
>> txeq-precode-en-g6 = <Host Lane 0 PrecodeEn, Device Lane 0 PrecodeEn, Host
>> Lane 1 PrecodeEn, Device Lane 1 PrecodeEn>;
>>
> How about encoding Host and Device values in a single tuple. Like,
>
> txeq-preshoot-g6 = <Lane_0 Host_PreShoot Device_PreShoot>, <Lane 1...>,
Man, I don't like that way to be honest, it took me a few minutes to
understand it on the PCIe side...
Let's go with my approach please...
Thanks,
Can Guo.
>
> - Mani
>
next prev parent reply other threads:[~2026-05-27 9:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260523134711.323425-1-can.guo@oss.qualcomm.com>
2026-05-23 13:47 ` Can Guo
2026-05-23 14:14 ` Manivannan Sadhasivam
2026-05-27 8:51 ` Can Guo
2026-05-27 9:15 ` Manivannan Sadhasivam
2026-05-27 9:24 ` Can Guo [this message]
2026-05-27 9:28 ` Can Guo
2026-05-23 13:47 ` [PATCH v2 2/2] scsi: ufs: core: Add support for static TX Equalization settings Can Guo
2026-05-23 14:15 ` Manivannan Sadhasivam
2026-05-27 8:51 ` Can Guo
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