Re: [PATCH 4/4] drm/msm/adreno: Add Adreno 620

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/16/26 2:53 PM, Ishu Brar via B4 Relay wrote:
> From: Ishu Brar <patches@brar.si>
> 
> Add the catalog entry for the Adreno 620 (chip id 0x06020000) found in
> the Snapdragon 765/765G/768G (SM7250). It is an A650 derivative and
> uses its SQE and GMU firmware and protect table, together with the A620
> zap shader.
> 
> The speed-bin fuse values map to the OPP bins as in the downstream
> "lito" devicetree: fuse 0 is the default bin and fuse 132 and 115 are
> the two alternate ones.
> 
> Tested on a OnePlus Nord (SM7250) with Vulkan.
> 
> Signed-off-by: Ishu Brar <patches@brar.si>
> ---

The protect maps differ a little, GPT says this:

- Downstream entry: {0x1c800, 0x1e7ff, NORDWR}.
- Mainline: NORDWR(0x1a800, 0x1fff) ends at 0x1c7ff. The next mainline entry is NORDWR(0x1f400, 0x443). So nothing covers 0x1c800–0x1e7ff.
- Registers there (from generated/a6xx_gmu.xml.h):
- GMU_NMI_CONTROL_STATUS (0x1cbf0)
- GMU_BOOT_SLUMBER_OPTION (0x1cbf8)
- GMU_GX_VOTE_IDX (0x1cbf9), GMU_MX_VOTE_IDX (0x1cbfa)
- GMU_DCVS_ACK_OPTION (0x1cbfc), GMU_DCVS_PERF_SETTING (0x1cbfd), GMU_DCVS_BW_SETTING (0x1cbfe), GMU_DCVS_RETURN (0x1cbff)
- GMU_CORE_FW_VERSION (0x1d3f8)

and it turns out that a650 should naturally reserve those too..

so please just add a

+	A6XX_PROTECT_NORDWR(0x1c800, 0x1fff),

in a separate commit there

Konrad