From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: patches@brar.si, Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Akhil P Oommen <akhilpo@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] drm/msm/a6xx: Add a bandwidth table for the Adreno 620 GMU
Date: Mon, 19 Oct 2026 14:38:50 +0200 [thread overview]
Message-ID: <577a1383-1198-484e-81cd-3de996cc7150@oss.qualcomm.com> (raw)
In-Reply-To: <20261016-adreno-a620-v1-2-4a7ed6210d7d@brar.si>
On 10/16/26 2:53 PM, Ishu Brar via B4 Relay wrote:
> From: Ishu Brar <patches@brar.si>
>
> Without an A620 specific table the GMU falls back to the generic A630
> one, whose BCM addresses do not exist on SM7250, and the first GX
> performance vote times out.
>
> Like the A650 one, send a single "off" entry just to get things running,
> with the BCM addresses looked up in cmd-db. Add adreno_is_a620() for the
> selection.
>
> Assisted-by: Claude
> Signed-off-by: Ishu Brar <patches@brar.si>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 6b34e704a..cab7ffc63 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -553,6 +553,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x60000001;
> }
>
> +static void a620_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
This is no longer necessary if you add .bcms in the catalog,
see a6xx_generate_bw_table()
Konrad
next prev parent reply other threads:[~2026-10-19 12:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 12:53 [PATCH 0/4] drm/msm/adreno: Add Adreno 620 Ishu Brar via B4 Relay
2026-10-16 12:53 ` [PATCH 1/4] dt-bindings: display: msm: Document Adreno 620 and its GMU Ishu Brar via B4 Relay
2026-10-17 17:47 ` Krzysztof Kozlowski
2026-10-16 12:53 ` [PATCH 2/4] drm/msm/a6xx: Add a bandwidth table for the Adreno 620 GMU Ishu Brar via B4 Relay
2026-10-19 12:38 ` Konrad Dybcio [this message]
2026-10-16 12:53 ` [PATCH 3/4] drm/msm/a6xx: Program the PDC sequencer on Adreno 620 Ishu Brar via B4 Relay
2026-10-19 13:12 ` Konrad Dybcio
2026-10-16 12:53 ` [PATCH 4/4] drm/msm/adreno: Add " Ishu Brar via B4 Relay
2026-10-19 13:23 ` Konrad Dybcio
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