[PATCH 0/7] dmaengine: xilinx_dma: MCDMA descriptor and metadata handling improvements

[PATCH 0/7] dmaengine: xilinx_dma: MCDMA descriptor and metadata handling improvements

[Srinivas Neeli]

This series improves the AXI MCDMA driver with fixes and enhancements for
descriptor handling and metadata reporting. The first patch fixes a bug
where the driver was using generic descriptor field names for both MM2S
and S2MM directions, even though the hardware uses different field layouts.
This could lead to incorrect residue calculations and descriptor
completion detection. The second patch updates device tree bindings to
move xlnx,irq-delay to the common section. The third patch adds proper
completion bit checking for MCDMA descriptors, which is essential when
interrupt delay timeout is enabled to avoid prematurely freeing
descriptors. Patches 4-7 extend metadata support for MCDMA. When the
AXI4-stream status/control interface is present, metadata is provided
through APP fields. When this interface is absent, the series adds support
for reporting transferred byte count through the status field, enabling
clients to track transfer progress in both configurations.

Device tree binding documentation is updated accordingly to support these
enhancements.

Srinivas Neeli (4):
  dmaengine: xilinx_dma: Fix MCDMA descriptor fields for MM2S vs S2MM
  dt-bindings: dmaengine: xilinx_dma: Move xlnx,irq-delay to common AXI
    DMA and MCDMA section
  dmaengine: xilinx_dma: Move descriptors to done list based on
    completion bit
  dt-bindings: xilinx-dma: Extend 'xlnx,axistream-connected' property to
    MCDMA

Suraj Gupta (3):
  dmaengine: xilinx_dma: Extend metadata handling for AXI MCDMA
  dt-bindings: dmaengine: xilinx_dma: Add "xlnx,include-stscntrl-strm"
    property
  dmaengine: xilinx_dma: Add support for reporting transfer size to AXI
    DMA / MCDMA client when app fields are unavailable

 .../bindings/dma/xilinx/xilinx_dma.txt        |  9 +-
 drivers/dma/xilinx/xilinx_dma.c               | 93 ++++++++++++++++---
 2 files changed, 86 insertions(+), 16 deletions(-)

-- 
2.25.1

[PATCH 1/7] dmaengine: xilinx_dma: Fix MCDMA descriptor fields for MM2S vs S2MM

[Srinivas Neeli]

The MCDMA BD format differs between MM2S and S2MM directions, but the
driver was using generic 'status' and 'sideband_status' fields for both.
This could lead to incorrect residue calculations when the hardware
updates direction-specific fields.

Refactor the descriptor structure to use unions with direction-specific
field names (mm2s_status/s2mm_status, etc.). This ensures the driver
accesses the correct hardware fields based on channel direction and
matches the hardware documentation.

Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support")
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
 drivers/dma/xilinx/xilinx_dma.c | 29 ++++++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 53229d8ebc52..e09a22721c01 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -275,8 +275,10 @@ struct xilinx_axidma_desc_hw {
  * @buf_addr_msb: MSB of Buffer address @0x0C
  * @rsvd: Reserved field @0x10
  * @control: Control Information field @0x14
- * @status: Status field @0x18
- * @sideband_status: Status of sideband signals @0x1C
+ * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18
+ * @s2mm_status: Status field for s2mm @0x18
+ * @mm2s_status: Status field for mm2s @0x1C
+ * @s2mm_sideband_status: Sideband status for s2mm @0x1C
  * @app: APP Fields @0x20 - 0x30
  */
 struct xilinx_aximcdma_desc_hw {
@@ -286,8 +288,14 @@ struct xilinx_aximcdma_desc_hw {
 	u32 buf_addr_msb;
 	u32 rsvd;
 	u32 control;
-	u32 status;
-	u32 sideband_status;
+	union {
+		u32 mm2s_ctrl_sideband;
+		u32 s2mm_status;
+	};
+	union {
+		u32 mm2s_status;
+		u32 s2mm_sideband_status;
+	};
 	u32 app[XILINX_DMA_NUM_APP_WORDS];
 } __aligned(64);
 
@@ -1013,9 +1021,16 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
 					   struct xilinx_aximcdma_tx_segment,
 					   node);
 			aximcdma_hw = &aximcdma_seg->hw;
-			residue +=
-				(aximcdma_hw->control - aximcdma_hw->status) &
-				chan->xdev->max_buffer_len;
+			if (chan->direction == DMA_DEV_TO_MEM)
+				residue +=
+					(aximcdma_hw->control -
+					 aximcdma_hw->s2mm_status) &
+					chan->xdev->max_buffer_len;
+			else
+				residue +=
+					(aximcdma_hw->control -
+					 aximcdma_hw->mm2s_status) &
+					chan->xdev->max_buffer_len;
 		}
 	}
 
-- 
2.25.1

[PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Move xlnx,irq-delay to common AXI DMA and MCDMA section

[Srinivas Neeli]

xlnx,irq-delay property is applicable to both AXI DMA and MCDMA
designs. Move it from "Optional properties for AXI DMA" to "Optional
properties for AXI DMA and MCDMA" section to correctly reflect its usage.

Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index b567107270cb..c9e75ce23d55 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -49,12 +49,12 @@ Optional properties for AXI DMA and MCDMA:
 	register as configured in h/w. Takes values {8...26}. If the property
 	is missing or invalid then the default value 23 is used. This is the
 	maximum value that is supported by all IP versions.
-
-Optional properties for AXI DMA:
-- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
 - xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
 	0-255. Setting this value to zero disables the delay timer interrupt.
 	1 timeout interval = 125 * clock period of SG clock.
+
+Optional properties for AXI DMA:
+- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1

[PATCH 3/7] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit

[Srinivas Neeli]

In AXIMCDMA scatter-gather mode, the hardware sets the completion bit when
a transfer finishes. The driver now checks this bit to free descriptors
from the active list and move them to the done list.
This is required when interrupt delay timeout Dly_IrqEn is enabled,
as interrupts may be triggered before the configured threshold is reached,
even if not all descriptors have completed.

Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
 drivers/dma/xilinx/xilinx_dma.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index e09a22721c01..e3f8c0f09a17 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1762,6 +1762,18 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
 					      struct xilinx_axidma_tx_segment, node);
 			if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
 				break;
+		} else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
+			struct xilinx_aximcdma_tx_segment *seg;
+			bool completed;
+
+			seg = list_last_entry(&desc->segments,
+					      struct xilinx_aximcdma_tx_segment,
+					      node);
+			completed = (chan->direction == DMA_DEV_TO_MEM) ?
+				(seg->hw.s2mm_status & XILINX_DMA_BD_COMP_MASK) :
+				(seg->hw.mm2s_status & XILINX_DMA_BD_COMP_MASK);
+			if (!completed)
+				break;
 		}
 		if (chan->has_sg && chan->xdev->dma_config->dmatype !=
 		    XDMA_TYPE_VDMA)
-- 
2.25.1

[PATCH 4/7] dt-bindings: xilinx-dma: Extend 'xlnx,axistream-connected' property to MCDMA

[Srinivas Neeli]

Extend the xlnx,axistream-connected property for MCDMA IP. MCDMA also
supports AXI-Stream based designs, so the same property can be used to
enable stream-specific behavior and metadata handling.

Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index c9e75ce23d55..cab66742e168 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -52,9 +52,10 @@ Optional properties for AXI DMA and MCDMA:
 - xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
 	0-255. Setting this value to zero disables the delay timer interrupt.
 	1 timeout interval = 125 * clock period of SG clock.
+- xlnx,axistream-connected: Tells whether DMA or MCDMA is connected to
+	AXI stream IP.
 
 Optional properties for AXI DMA:
-- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1

[PATCH 5/7] dmaengine: xilinx_dma: Extend metadata handling for AXI MCDMA

[Srinivas Neeli]

From: Suraj Gupta <suraj.gupta2@amd.com>

Extend probe logic to detect AXI Stream connections for MCDMA. When
an AXI Stream interface is present, metadata operations are enabled for
the MCDMA channel. The xilinx_dma_get_metadata_ptr() is enhanced to
retrieve metadata directly from MCDMA descriptors.
Add corresponding channel reference in struct xilinx_dma_tx_descriptor to
retrieve associated channel.
These changes ensure proper metadata handling and accurate transfer
size reporting for MCDMA transfers.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
Co-developed-by: Srinivas Neeli <srinivas.neeli@amd.com>
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
 drivers/dma/xilinx/xilinx_dma.c | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index e3f8c0f09a17..0fed6bb1b354 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -222,6 +222,8 @@
 #define XILINX_MCDMA_BD_EOP			BIT(30)
 #define XILINX_MCDMA_BD_SOP			BIT(31)
 
+struct xilinx_dma_chan;
+
 /**
  * struct xilinx_vdma_desc_hw - Hardware Descriptor
  * @next_desc: Next Descriptor Pointer @0x00
@@ -371,6 +373,7 @@ struct xilinx_cdma_tx_segment {
 
 /**
  * struct xilinx_dma_tx_descriptor - Per Transaction structure
+ * @chan: DMA channel for which this descriptor is allocated
  * @async_tx: Async transaction descriptor
  * @segments: TX segments list
  * @node: Node in the channel descriptors list
@@ -379,6 +382,7 @@ struct xilinx_cdma_tx_segment {
  * @residue: Residue of the completed descriptor
  */
 struct xilinx_dma_tx_descriptor {
+	struct xilinx_dma_chan *chan;
 	struct dma_async_tx_descriptor async_tx;
 	struct list_head segments;
 	struct list_head node;
@@ -653,12 +657,23 @@ static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,
 					 size_t *payload_len, size_t *max_len)
 {
 	struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
-	struct xilinx_axidma_tx_segment *seg;
+	void *metadata_ptr;
+
+	if (desc->chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
+		struct xilinx_aximcdma_tx_segment *seg;
 
+		seg = list_first_entry(&desc->segments,
+				       struct xilinx_aximcdma_tx_segment, node);
+		metadata_ptr = seg->hw.app;
+	} else {
+		struct xilinx_axidma_tx_segment *seg;
+
+		seg = list_first_entry(&desc->segments,
+				       struct xilinx_axidma_tx_segment, node);
+		metadata_ptr = seg->hw.app;
+	}
 	*max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
-	seg = list_first_entry(&desc->segments,
-			       struct xilinx_axidma_tx_segment, node);
-	return seg->hw.app;
+	return metadata_ptr;
 }
 
 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
@@ -848,6 +863,7 @@ xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
 	if (!desc)
 		return NULL;
 
+	desc->chan = chan;
 	INIT_LIST_HEAD(&desc->segments);
 
 	return desc;
@@ -2613,6 +2629,9 @@ xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
 		segment->hw.control |= XILINX_MCDMA_BD_EOP;
 	}
 
+	if (chan->xdev->has_axistream_connected)
+		desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
+
 	return &desc->async_tx;
 
 error:
@@ -3261,7 +3280,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 
 	dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len);
 
-	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
+	    xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
 		xdev->has_axistream_connected =
 			of_property_read_bool(node, "xlnx,axistream-connected");
 	}
-- 
2.25.1

[PATCH 6/7] dt-bindings: dmaengine: xilinx_dma: Add "xlnx,include-stscntrl-strm" property

[Srinivas Neeli]

From: Suraj Gupta <suraj.gupta2@amd.com>

Add an optional boolean DT property "xlnx,include-stscntrl-strm" to
indicate that the AXI DMA IP is configured with the AXI4-Stream status
and control interface. This enables the use of APP fields in DMA
descriptors for metadata reporting.

This property is distinct from "xlnx,axistream-connected" and serves a
different purpose:

- "xlnx,include-stscntrl-strm": Indicates whether APP fields are present
  in DMA descriptors. When enabled, the driver can access status/control
  metadata through these descriptor fields.

- "xlnx,axistream-connected": Indicates whether a streaming IP (client)
  is connected to the DMA IP.

These two configurations are independent of each other. For example, in
TSN (Time-Sensitive Networking) designs, a streaming client may be
connected to the DMA IP, but the status/control stream interface is not
enabled. In such cases, "xlnx,axistream-connected" would be present while
"xlnx,include-stscntrl-strm" would be absent.

Adding this property allows the driver to correctly determine descriptor
layout and access APP fields only when the hardware supports them.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index cab66742e168..e72f1bb5a520 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -56,6 +56,8 @@ Optional properties for AXI DMA and MCDMA:
 	AXI stream IP.
 
 Optional properties for AXI DMA:
+- xlnx,include-stscntrl-strm: Tells hardware is configured with AXI4-stream
+	status and control interface.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1

[PATCH 7/7] dmaengine: xilinx_dma: Add support for reporting transfer size to AXI DMA / MCDMA client when app fields are unavailable

[Srinivas Neeli]

From: Suraj Gupta <suraj.gupta2@amd.com>

The AXI4-stream status and control interface is optional in the AXI DMA /
MCDMA IP design; when it is not present, app fields are not available in
DMA descriptor. In such cases, the transferred byte count can be
communicated to the client using the status field (bits 0-25) of
AXI DMA / MCDMA descriptor.

Add a xferred_bytes field to struct xilinx_dma_tx_descriptor to record the
number of bytes transferred for each transaction. The value is calculated
using the existing xilinx_dma_get_residue() function, which traverses all
hardware descriptors associated with the async transaction descriptor,
avoiding redundant traversal.

The driver uses the xlnx,include-stscntrl-strm device tree property to
determine if the status/control stream interface is present and selects the
appropriate metadata source accordingly.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 drivers/dma/xilinx/xilinx_dma.c | 28 ++++++++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 0fed6bb1b354..651a360a0afd 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -380,6 +380,8 @@ struct xilinx_cdma_tx_segment {
  * @cyclic: Check for cyclic transfers.
  * @err: Whether the descriptor has an error.
  * @residue: Residue of the completed descriptor
+ * @xferred_bytes: Number of bytes transferred by this transaction
+ *                 descriptor.
  */
 struct xilinx_dma_tx_descriptor {
 	struct xilinx_dma_chan *chan;
@@ -389,6 +391,7 @@ struct xilinx_dma_tx_descriptor {
 	bool cyclic;
 	bool err;
 	u32 residue;
+	u32 xferred_bytes;
 };
 
 /**
@@ -515,6 +518,7 @@ struct xilinx_dma_config {
  * @mm2s_chan_id: DMA mm2s channel identifier
  * @max_buffer_len: Max buffer length
  * @has_axistream_connected: AXI DMA connected to AXI Stream IP
+ * @has_stsctrl_stream: AXI4-stream status and control interface is enabled
  */
 struct xilinx_dma_device {
 	void __iomem *regs;
@@ -534,6 +538,7 @@ struct xilinx_dma_device {
 	u32 mm2s_chan_id;
 	u32 max_buffer_len;
 	bool has_axistream_connected;
+	bool has_stsctrl_stream;
 };
 
 /* Macros */
@@ -672,8 +677,12 @@ static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,
 				       struct xilinx_axidma_tx_segment, node);
 		metadata_ptr = seg->hw.app;
 	}
-	*max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
-	return metadata_ptr;
+	if (desc->chan->xdev->has_stsctrl_stream) {
+		*max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
+		return metadata_ptr;
+	}
+	*max_len = *payload_len = sizeof(desc->xferred_bytes);
+	return (void *)&desc->xferred_bytes;
 }
 
 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
@@ -864,6 +873,7 @@ xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
 		return NULL;
 
 	desc->chan = chan;
+	desc->xferred_bytes = 0;
 	INIT_LIST_HEAD(&desc->segments);
 
 	return desc;
@@ -1014,6 +1024,7 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
 	struct xilinx_aximcdma_desc_hw *aximcdma_hw;
 	struct list_head *entry;
 	u32 residue = 0;
+	u32 xferred = 0;
 
 	list_for_each(entry, &desc->segments) {
 		if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
@@ -1031,25 +1042,32 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
 			axidma_hw = &axidma_seg->hw;
 			residue += (axidma_hw->control - axidma_hw->status) &
 				   chan->xdev->max_buffer_len;
+			xferred += axidma_hw->status & chan->xdev->max_buffer_len;
 		} else {
 			aximcdma_seg =
 				list_entry(entry,
 					   struct xilinx_aximcdma_tx_segment,
 					   node);
 			aximcdma_hw = &aximcdma_seg->hw;
-			if (chan->direction == DMA_DEV_TO_MEM)
+			if (chan->direction == DMA_DEV_TO_MEM) {
 				residue +=
 					(aximcdma_hw->control -
 					 aximcdma_hw->s2mm_status) &
 					chan->xdev->max_buffer_len;
-			else
+				xferred += aximcdma_hw->s2mm_status &
+					chan->xdev->max_buffer_len;
+			} else {
 				residue +=
 					(aximcdma_hw->control -
 					 aximcdma_hw->mm2s_status) &
 					chan->xdev->max_buffer_len;
+				xferred += aximcdma_hw->mm2s_status &
+					chan->xdev->max_buffer_len;
+			}
 		}
 	}
 
+	desc->xferred_bytes = xferred;
 	return residue;
 }
 
@@ -3284,6 +3302,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 	    xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
 		xdev->has_axistream_connected =
 			of_property_read_bool(node, "xlnx,axistream-connected");
+		xdev->has_stsctrl_stream =
+			of_property_read_bool(node, "xlnx,include-stscntrl-strm");
 	}
 
 	if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
-- 
2.25.1

Re: [PATCH 6/7] dt-bindings: dmaengine: xilinx_dma: Add "xlnx,include-stscntrl-strm" property

[Krzysztof Kozlowski]

On 12/02/2026 14:51, Srinivas Neeli wrote:
> From: Suraj Gupta <suraj.gupta2@amd.com>
> 
> Add an optional boolean DT property "xlnx,include-stscntrl-strm" to
> indicate that the AXI DMA IP is configured with the AXI4-Stream status
> and control interface. This enables the use of APP fields in DMA
> descriptors for metadata reporting.

Changes to TXT bindings are not allowed for long time. Convert the
bindings first.

Best regards,
Krzysztof

Re: [PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Move xlnx,irq-delay to common AXI DMA and MCDMA section

[Krzysztof Kozlowski]

On 12/02/2026 14:51, Srinivas Neeli wrote:
> xlnx,irq-delay property is applicable to both AXI DMA and MCDMA
> designs. Move it from "Optional properties for AXI DMA" to "Optional
> properties for AXI DMA and MCDMA" section to correctly reflect its usage.
> 
> Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
> ---
>  Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 


First convert the binding, then make changes to it.

Best regards,
Krzysztof