[PATCH v3 0/3] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.

[PATCH v3 0/3] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.

[Petko Manolov]

Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the same
carrier and they are cross-monitoring each other.

This is the SoCFPGA devicetree part.

Changes in v3:

  - add Draeger AG in devicetree/bindings/vendor-prefixes.yaml
  - separate binding changes from the actual devicetree patch
  - remove "earlyprintk" from the boot arguments

Petko Manolov (3):
  Add Draeger AG as a vendor
  Add Draeger's M48 board to the SoCFPGA family.
  Add socfpga devicetree for Draeger's M48 board.

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
 .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 129 ++++++++++++++++++
 4 files changed, 133 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts

-- 
2.47.3

[PATCH v3 1/3] Add Draeger AG as a vendor

[Petko Manolov]

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969373..276d62b848d5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -467,6 +467,8 @@ patternProperties:
     description: DPTechnics
   "^dptel,.*":
     description: Guangdong Dapu Telecom Co., Ltd.
+  "^draeger,.*":
+    description: Draegerwerk AG & Co. KGaA
   "^dragino,.*":
     description: Dragino Technology Co., Limited
   "^dream,.*":
-- 
2.47.3

Re: [PATCH v3 1/3] Add Draeger AG as a vendor

[Krzysztof Kozlowski]

On Wed, Sep 09, 2026 at 02:15:09PM +0300, Petko Manolov wrote:
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)

I don't see improvements, so previous review is still valid.

Best regards,
Krzysztof

[PATCH v3 2/3] Add Draeger's M48 board to the SoCFPGA family.

[Petko Manolov]

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/arm/altera.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 3030cf46fe74..8ed1ba733510 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -47,6 +47,7 @@ properties:
           - enum:
               - altr,socfpga-cyclone5-socdk
               - denx,mcvevk
+              - draeger,M48
               - ebv,socrates
               - macnica,sodia
               - novtech,chameleon96
-- 
2.47.3

Re: [PATCH v3 2/3] Add Draeger's M48 board to the SoCFPGA family.

[Krzysztof Kozlowski]

On Wed, Sep 09, 2026 at 02:15:10PM +0300, Petko Manolov wrote:
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
> ---
>  Documentation/devicetree/bindings/arm/altera.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Same review... Actually, even more - subject is completely odd. This is
not a sentence (just use `git log` to learn that) and you completely
missed prefixes. Again git log.

Best regards,
Krzysztof

[PATCH v3 3/3] Add socfpga devicetree for Draeger's M48 board.

[Petko Manolov]

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
 .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 129 ++++++++++++++++++
 2 files changed, 130 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts

diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
index 8df0976da01c..cdcea11abdfa 100644
--- a/arch/arm/boot/dts/intel/socfpga/Makefile
+++ b/arch/arm/boot/dts/intel/socfpga/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
 	socfpga_arria10_mercury_aa1_st1_emmc.dtb \
 	socfpga_arria10_mercury_aa1_st1_qspi.dtb \
 	socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
+	socfpga_cyclone5_draeger_m48.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
 	socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
new file mode 100644
index 000000000000..6c5a8013d40c
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ */
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Draeger M48 Cyclone V SoC";
+	compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+
+		/* 1GB */
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac0 device tree blob.
+		 */
+		ethernet0 = &gmac0;
+	};
+
+	soc {
+		gpio3: gpio@ff202000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff202000 0x20>;
+			status = "okay";
+
+			portd: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <2>;
+				reg = <0>;
+				bank-name = "SYNC_I";
+			};
+		};
+
+		gpio4: gpio@ff202020 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff202020 0x20>;
+			status = "okay";
+
+			porte: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <2>;
+				reg = <0>;
+				bank-name = "SYNC_O";
+			};
+		};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	rxc-skew-ps = <1860>;
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	rxdv-skew-ps = <0>;
+	txc-skew-ps = <900>;
+	txd0-skew-ps = <0>;
+	txd1-skew-ps = <0>;
+	txd2-skew-ps = <0>;
+	txd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	eeprom_mac: eeprom@50 {
+		compatible = "atmel,24c08";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&mmc0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <0>;
+
+		/* chip select */
+		spi-max-frequency = <100000000>;
+		m25p,fast-read;
+		cdns,read-delay = <4>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+	};
+};
-- 
2.47.3

Re: [PATCH v3 3/3] Add socfpga devicetree for Draeger's M48 board.

[Dinh Nguyen]

On 9/9/26 06:15, Petko Manolov wrote:
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
> ---
>   arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
>   .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 129 ++++++++++++++++++
>   2 files changed, 130 insertions(+)
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> 
> diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
> index 8df0976da01c..cdcea11abdfa 100644
> --- a/arch/arm/boot/dts/intel/socfpga/Makefile
> +++ b/arch/arm/boot/dts/intel/socfpga/Makefile
> @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
>   	socfpga_arria10_mercury_aa1_st1_emmc.dtb \
>   	socfpga_arria10_mercury_aa1_st1_qspi.dtb \
>   	socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
> +	socfpga_cyclone5_draeger_m48.dtb \
>   	socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
>   	socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
>   	socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> new file mode 100644
> index 000000000000..6c5a8013d40c
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  (C) Copyright 2020 Draeger and Licensors, info@draeger.com
> + */
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> +	model = "Draeger M48 Cyclone V SoC";
> +	compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@0 {
> +		name = "memory";
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>;
> +
> +		/* 1GB */

Stray comment?

> +	};
> +
> +	aliases {
> +		/* this allow the ethaddr uboot environmnet variable contents
> +		 * to be added to the gmac0 device tree blob.
> +		 */
> +		ethernet0 = &gmac0;
> +	};
> +
> +	soc {
> +		gpio3: gpio@ff202000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0xff202000 0x20>;
> +			status = "okay";
> +
> +			portd: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				snps,nr-gpios = <2>;
> +				reg = <0>;
> +				bank-name = "SYNC_I";

bank-name? I don't see it documented anywhere.


Dinh

Re: [PATCH v3 3/3] Add socfpga devicetree for Draeger's M48 board.

[Petko Manolov]

On 26-09-09 08:36:14, Dinh Nguyen wrote:
> 
> On 9/9/26 06:15, Petko Manolov wrote:
> >
> > +				bank-name = "SYNC_I";
> 
> bank-name? I don't see it documented anywhere.

These DTs come from u-boot where it is documented.  What would be the correct
approach: to drop the property or document it?


		Petko

Re: [PATCH v3 3/3] Add socfpga devicetree for Draeger's M48 board.

[Dinh Nguyen]

On 9/11/26 04:25, Petko Manolov wrote:
> On 26-09-09 08:36:14, Dinh Nguyen wrote:
>>
>> On 9/9/26 06:15, Petko Manolov wrote:
>>>
>>> +				bank-name = "SYNC_I";
>>
>> bank-name? I don't see it documented anywhere.
> 
> These DTs come from u-boot where it is documented.  What would be the correct
> approach: to drop the property or document it?
> 

DTs come from Linux, not the other way around. I don't see "bank-name" 
documented anywhere in the bindings document :
Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml

I don't see how the property is getting used in the driver.

Dinh

Re: [PATCH v3 3/3] Add socfpga devicetree for Draeger's M48 board.

[Petko Manolov]

On 26-09-11 04:54:21, Dinh Nguyen wrote:
> 
> 
> On 9/11/26 04:25, Petko Manolov wrote:
> > On 26-09-09 08:36:14, Dinh Nguyen wrote:
> > > 
> > > On 9/9/26 06:15, Petko Manolov wrote:
> > > > 
> > > > +				bank-name = "SYNC_I";
> > > 
> > > bank-name? I don't see it documented anywhere.
> > 
> > These DTs come from u-boot where it is documented.  What would be the
> > correct approach: to drop the property or document it?
> > 
> 
> DTs come from Linux, not the other way around. I don't see "bank-name"

I was explaining the origin of "bank-name", not that we should reverse the
process.

> I don't see how the property is getting used in the driver.

This is enough as a clue.  I'll just drop the property.


		Petko

Re: [PATCH v3 3/3] Add socfpga devicetree for Draeger's M48 board.

[Krzysztof Kozlowski]

On Wed, Sep 09, 2026 at 02:15:11PM +0300, Petko Manolov wrote:
> +
> +	aliases {
> +		/* this allow the ethaddr uboot environmnet variable contents
> +		 * to be added to the gmac0 device tree blob.
> +		 */
> +		ethernet0 = &gmac0;
> +	};
> +
> +	soc {
> +		gpio3: gpio@ff202000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0xff202000 0x20>;
> +			status = "okay";

Where was it disabled? Drop.

Best regards,
Krzysztof

Re: [PATCH v3 0/3] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.

[Dinh Nguyen]

Hi Petko,

On 9/9/26 06:15, Petko Manolov wrote:
> Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
> SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the same
> carrier and they are cross-monitoring each other.
> 
> This is the SoCFPGA devicetree part.
> 
> Changes in v3:
> 
>    - add Draeger AG in devicetree/bindings/vendor-prefixes.yaml
>    - separate binding changes from the actual devicetree patch
>    - remove "earlyprintk" from the boot arguments
> 
> Petko Manolov (3):
>    Add Draeger AG as a vendor
>    Add Draeger's M48 board to the SoCFPGA family.
>    Add socfpga devicetree for Draeger's M48 board.
> 
>   .../devicetree/bindings/arm/altera.yaml       |   1 +
>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>   arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
>   .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 129 ++++++++++++++++++
>   4 files changed, 133 insertions(+)
>   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> 

Please look up what a commit header and message should look like for 
these patches. For example:

patch 1/3 should look something like this:

dt-bindings: vendor-prefixes: add Draeger AG

Add a vendor prefix for Draegar AG, which is Draegerwerk AG & Co. KGaA

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>

You should look what the formatting of the commit header and message 
look like for the subsystem you're submitting patches to.

All of your patches are missing the appropriate formatting.

Dinh

Re: [PATCH v3 0/3] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.

[Petko Manolov]

On 26-09-09 08:27:22, Dinh Nguyen wrote:
> Hi Petko,
> 
> On 9/9/26 06:15, Petko Manolov wrote:
> > Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
> > SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the same
> > carrier and they are cross-monitoring each other.
> > 
> > This is the SoCFPGA devicetree part.
> > 
> > Changes in v3:
> > 
> >    - add Draeger AG in devicetree/bindings/vendor-prefixes.yaml
> >    - separate binding changes from the actual devicetree patch
> >    - remove "earlyprintk" from the boot arguments
> > 
> > Petko Manolov (3):
> >    Add Draeger AG as a vendor
> >    Add Draeger's M48 board to the SoCFPGA family.
> >    Add socfpga devicetree for Draeger's M48 board.
> > 
> >   .../devicetree/bindings/arm/altera.yaml       |   1 +
> >   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
> >   arch/arm/boot/dts/intel/socfpga/Makefile      |   1 +
> >   .../socfpga/socfpga_cyclone5_draeger_m48.dts  | 129 ++++++++++++++++++
> >   4 files changed, 133 insertions(+)
> >   create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> > 
> 
> Please look up what a commit header and message should look like for these
> patches. For example:
> 
> patch 1/3 should look something like this:
> 
> dt-bindings: vendor-prefixes: add Draeger AG
> 
> Add a vendor prefix for Draegar AG, which is Draegerwerk AG & Co. KGaA
> 
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>

That was really dump omission on my part, sorry.  Will be fixed.

> You should look what the formatting of the commit header and message look like
> for the subsystem you're submitting patches to.
> 
> All of your patches are missing the appropriate formatting.

Could you please specify.  I've run all of them through checkpatch.pl.  Maybe
i'm missing something else?


		Petko