* [PATCH V2 1/5] firmware: xilinx: Add ZynqMP efuse access API
2023-10-19 6:06 [PATCH V2 0/5] Add ZynqMP efuse access support Praveen Teja Kundanala
@ 2023-10-19 6:06 ` Praveen Teja Kundanala
2023-10-19 6:06 ` [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml Praveen Teja Kundanala
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Praveen Teja Kundanala @ 2023-10-19 6:06 UTC (permalink / raw)
To: srinivas.kandagatla, robh+dt, krzysztof.kozlowski+dt, conor+dt,
michal.simek, praveent, devicetree, linux-arm-kernel
Cc: linux-kernel
Add zynqmp_pm_efuse_access API in the ZynqMP
firmware for read/write access of efuse memory.
Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
---
drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
2 files changed, 33 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 4cc1ac7f76ed..5a4f7256b9e7 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -3,6 +3,7 @@
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2022 Xilinx, Inc.
+ * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Davorin Mista <davorin.mista@aggios.com>
@@ -1435,6 +1436,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
+/**
+ * zynqmp_pm_efuse_access - Provides access to efuse memory.
+ * @address: Address of the efuse params structure
+ * @out: Returned output value
+ *
+ * Return: Returns status, either success or error code.
+ */
+int zynqmp_pm_efuse_access(const u64 address, u32 *out)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!out)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, upper_32_bits(address),
+ lower_32_bits(address), 0, 0,
+ ret_payload);
+ *out = ret_payload[1];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access);
+
/**
* zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
* @address: Address of the data/ Address of output buffer where
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index e8b12ec8b060..4f574fab74eb 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -3,6 +3,7 @@
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2021 Xilinx
+ * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Davorin Mista <davorin.mista@aggios.com>
@@ -143,6 +144,7 @@ enum pm_api_id {
PM_CLOCK_GETPARENT = 44,
PM_FPGA_READ = 46,
PM_SECURE_AES = 47,
+ PM_EFUSE_ACCESS = 53,
PM_FEATURE_CHECK = 63,
};
@@ -534,6 +536,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
+int zynqmp_pm_efuse_access(const u64 address, u32 *out);
int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_get_status(u32 *value);
@@ -727,6 +730,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
return -ENODEV;
}
+static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
const u32 flags)
{
--
2.36.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
2023-10-19 6:06 [PATCH V2 0/5] Add ZynqMP efuse access support Praveen Teja Kundanala
2023-10-19 6:06 ` [PATCH V2 1/5] firmware: xilinx: Add ZynqMP efuse access API Praveen Teja Kundanala
@ 2023-10-19 6:06 ` Praveen Teja Kundanala
2023-10-19 9:26 ` Krzysztof Kozlowski
2023-10-19 6:06 ` [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes Praveen Teja Kundanala
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Praveen Teja Kundanala @ 2023-10-19 6:06 UTC (permalink / raw)
To: srinivas.kandagatla, robh+dt, krzysztof.kozlowski+dt, conor+dt,
michal.simek, praveent, devicetree, linux-arm-kernel
Cc: linux-kernel
Convert the xlnx,zynqmp-nvmem.txt to yaml.
Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 -------------------
.../bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 40 ++++++++++++++++
2 files changed, 40 insertions(+), 46 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
deleted file mode 100644
index 4881561b3a02..000000000000
--- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
+++ /dev/null
@@ -1,46 +0,0 @@
---------------------------------------------------------------------------
-= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
---------------------------------------------------------------------------
-The nvmem_firmware node provides access to the hardware related data
-like soc revision, IDCODE... etc, By using the firmware interface.
-
-Required properties:
-- compatible: should be "xlnx,zynqmp-nvmem-fw"
-
-= Data cells =
-Are child nodes of silicon id, bindings of which as described in
-bindings/nvmem/nvmem.txt
-
--------
- Example
--------
-firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- method = "smc";
-
- nvmem_firmware {
- compatible = "xlnx,zynqmp-nvmem-fw";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* Data cells */
- soc_revision: soc_revision {
- reg = <0x0 0x4>;
- };
- };
- };
-};
-
-= Data consumers =
-Are device nodes which consume nvmem data cells.
-
-For example:
- pcap {
- ...
-
- nvmem-cells = <&soc_revision>;
- nvmem-cell-names = "soc_revision";
-
- ...
- };
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
new file mode 100644
index 000000000000..5d20362a0615
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
+
+description: |
+ The ZynqMP MPSoC provides access to the hardware related data
+ like SOC revision, IDCODE and specific purpose efuses.
+
+maintainers:
+ - Kalyani Akula <kalyani.akula@amd.com>
+ - Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
+
+allOf:
+ - $ref: nvmem.yaml#
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-nvmem-fw
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nvmem-firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc-revision@0 {
+ reg = <0x0 0x4>;
+ };
+ };
--
2.36.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
2023-10-19 6:06 ` [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml Praveen Teja Kundanala
@ 2023-10-19 9:26 ` Krzysztof Kozlowski
2023-10-19 10:35 ` Kundanala, Praveen Teja
0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-19 9:26 UTC (permalink / raw)
To: Praveen Teja Kundanala, srinivas.kandagatla, robh+dt,
krzysztof.kozlowski+dt, conor+dt, michal.simek, praveent,
devicetree, linux-arm-kernel
Cc: linux-kernel
On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
> Convert the xlnx,zynqmp-nvmem.txt to yaml.
>
> Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> ---
> .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 -------------------
> .../bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 40 ++++++++++++++++
> 2 files changed, 40 insertions(+), 46 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
>
> diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> deleted file mode 100644
> index 4881561b3a02..000000000000
> --- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> +++ /dev/null
> @@ -1,46 +0,0 @@
> ---------------------------------------------------------------------------
> -= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
> ---------------------------------------------------------------------------
> -The nvmem_firmware node provides access to the hardware related data
> -like soc revision, IDCODE... etc, By using the firmware interface.
> -
> -Required properties:
> -- compatible: should be "xlnx,zynqmp-nvmem-fw"
> -
> -= Data cells =
> -Are child nodes of silicon id, bindings of which as described in
> -bindings/nvmem/nvmem.txt
> -
> --------
> - Example
> --------
> -firmware {
> - zynqmp_firmware: zynqmp-firmware {
> - compatible = "xlnx,zynqmp-firmware";
> - method = "smc";
> -
> - nvmem_firmware {
> - compatible = "xlnx,zynqmp-nvmem-fw";
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - /* Data cells */
> - soc_revision: soc_revision {
> - reg = <0x0 0x4>;
> - };
> - };
> - };
> -};
> -
> -= Data consumers =
> -Are device nodes which consume nvmem data cells.
> -
> -For example:
> - pcap {
> - ...
> -
> - nvmem-cells = <&soc_revision>;
> - nvmem-cell-names = "soc_revision";
> -
> - ...
> - };
> diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
> new file mode 100644
> index 000000000000..5d20362a0615
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
> +
> +description: |
> + The ZynqMP MPSoC provides access to the hardware related data
> + like SOC revision, IDCODE and specific purpose efuses.
> +
> +maintainers:
> + - Kalyani Akula <kalyani.akula@amd.com>
> + - Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> +
> +allOf:
> + - $ref: nvmem.yaml#
> +
> +properties:
> + compatible:
> + const: xlnx,zynqmp-nvmem-fw
> +
> +required:
> + - compatible
Test your bindings before sending. I am not a free tester of your
code... It's your duty.
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + nvmem-firmware {
Node names should be generic, so "nvmem". See also an explanation and
list of examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
I already asked for this.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread* RE: [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
2023-10-19 9:26 ` Krzysztof Kozlowski
@ 2023-10-19 10:35 ` Kundanala, Praveen Teja
0 siblings, 0 replies; 11+ messages in thread
From: Kundanala, Praveen Teja @ 2023-10-19 10:35 UTC (permalink / raw)
To: Krzysztof Kozlowski, srinivas.kandagatla, robh+dt,
krzysztof.kozlowski+dt, conor+dt, Simek, Michal, devicetree,
linux-arm-kernel
Cc: linux-kernel
[AMD Official Use Only - General]
Hi Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Thursday, October 19, 2023 2:57 PM
> To: Kundanala, Praveen Teja <praveen.teja.kundanala@amd.com>;
> srinivas.kandagatla@linaro.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; Simek, Michal
> <michal.simek@amd.com>; Kundanala, Praveen Teja
> <praveen.teja.kundanala@amd.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Subject: Re: [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-
> nvmem.txt to yaml
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
> > Convert the xlnx,zynqmp-nvmem.txt to yaml.
> >
> > Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> > ---
> > .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 -------------------
> > .../bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 40 ++++++++++++++++
> > 2 files changed, 40 insertions(+), 46 deletions(-) delete mode
> > 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-
> nvmem.txt
> > create mode 100644
> > Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> > b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> > deleted file mode 100644
> > index 4881561b3a02..000000000000
> > --- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> > +++ /dev/null
> > @@ -1,46 +0,0 @@
> > ----------------------------------------------------------------------
> > ----- -= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
> > ----------------------------------------------------------------------
> > ----- -The nvmem_firmware node provides access to the hardware related
> > data -like soc revision, IDCODE... etc, By using the firmware
> > interface.
> > -
> > -Required properties:
> > -- compatible: should be "xlnx,zynqmp-nvmem-fw"
> > -
> > -= Data cells =
> > -Are child nodes of silicon id, bindings of which as described in
> > -bindings/nvmem/nvmem.txt
> > -
> > --------
> > - Example
> > --------
> > -firmware {
> > - zynqmp_firmware: zynqmp-firmware {
> > - compatible = "xlnx,zynqmp-firmware";
> > - method = "smc";
> > -
> > - nvmem_firmware {
> > - compatible = "xlnx,zynqmp-nvmem-fw";
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > -
> > - /* Data cells */
> > - soc_revision: soc_revision {
> > - reg = <0x0 0x4>;
> > - };
> > - };
> > - };
> > -};
> > -
> > -= Data consumers =
> > -Are device nodes which consume nvmem data cells.
> > -
> > -For example:
> > - pcap {
> > - ...
> > -
> > - nvmem-cells = <&soc_revision>;
> > - nvmem-cell-names = "soc_revision";
> > -
> > - ...
> > - };
> > diff --git
> > a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
> > b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
> > new file mode 100644
> > index 000000000000..5d20362a0615
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-
> nvmem.yaml
> > @@ -0,0 +1,40 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
> > +
> > +description: |
> > + The ZynqMP MPSoC provides access to the hardware related data
> > + like SOC revision, IDCODE and specific purpose efuses.
> > +
> > +maintainers:
> > + - Kalyani Akula <kalyani.akula@amd.com>
> > + - Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> > +
> > +allOf:
> > + - $ref: nvmem.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: xlnx,zynqmp-nvmem-fw
> > +
> > +required:
> > + - compatible
>
> Test your bindings before sending. I am not a free tester of your code... It's your
> duty.
[Kundanala, Praveen Teja] Missed it will send V3 after testing.
>
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + nvmem-firmware {
>
> Node names should be generic, so "nvmem". See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-
> basics.html#generic-names-recommendation
>
> I already asked for this.
[Kundanala, Praveen Teja] Will refer and update it.
Regards,
Praveen
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
2023-10-19 6:06 [PATCH V2 0/5] Add ZynqMP efuse access support Praveen Teja Kundanala
2023-10-19 6:06 ` [PATCH V2 1/5] firmware: xilinx: Add ZynqMP efuse access API Praveen Teja Kundanala
2023-10-19 6:06 ` [PATCH V2 2/5] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml Praveen Teja Kundanala
@ 2023-10-19 6:06 ` Praveen Teja Kundanala
2023-10-19 9:27 ` Krzysztof Kozlowski
2023-10-19 6:06 ` [PATCH V2 4/5] nvmem: zynqmp_nvmem: Add support to access efuse Praveen Teja Kundanala
2023-10-19 6:06 ` [PATCH V2 5/5] MAINTAINERS: Add maintainers for ZynqMP NVMEM driver Praveen Teja Kundanala
4 siblings, 1 reply; 11+ messages in thread
From: Praveen Teja Kundanala @ 2023-10-19 6:06 UTC (permalink / raw)
To: srinivas.kandagatla, robh+dt, krzysztof.kozlowski+dt, conor+dt,
michal.simek, praveent, devicetree, linux-arm-kernel
Cc: linux-kernel
Add nvmem DT nodes for ZynqMP SOC
Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59 +++++++++++++++++++++++++-
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index b61fc99cd911..b7433e6b9d6c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
mbox-names = "tx", "rx";
};
- nvmem_firmware {
+ nvmem-firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
- soc_revision: soc_revision@0 {
+ soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
+ /* efuse access */
+ efuse_dna: efuse-dna@c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0@20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1@24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2@28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3@2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4@30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5@34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6@38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7@3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr@40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash@50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc@54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec@58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid@5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_aeskey: efuse-aeskey@60 {
+ reg = <0x60 0x20>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
+ reg = <0xd0 0x30>;
+ };
+ efuse_pufuser: efuse-pufuser@100 {
+ reg = <0x100 0x7F>;
+ };
};
zynqmp_pcap: pcap {
--
2.36.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
2023-10-19 6:06 ` [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes Praveen Teja Kundanala
@ 2023-10-19 9:27 ` Krzysztof Kozlowski
2023-10-19 10:32 ` Kundanala, Praveen Teja
0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-19 9:27 UTC (permalink / raw)
To: Praveen Teja Kundanala, srinivas.kandagatla, robh+dt,
krzysztof.kozlowski+dt, conor+dt, michal.simek, praveent,
devicetree, linux-arm-kernel
Cc: linux-kernel
On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
> Add nvmem DT nodes for ZynqMP SOC
>
> Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59 +++++++++++++++++++++++++-
> 1 file changed, 57 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index b61fc99cd911..b7433e6b9d6c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
> mbox-names = "tx", "rx";
> };
>
> - nvmem_firmware {
> + nvmem-firmware {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> compatible = "xlnx,zynqmp-nvmem-fw";
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> #address-cells = <1>;
> #size-cells = <1>;
>
> - soc_revision: soc_revision@0 {
> + soc_revision: soc-revision@0 {
> reg = <0x0 0x4>;
> };
Wasn't this fixed already by Michal?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread* RE: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
2023-10-19 9:27 ` Krzysztof Kozlowski
@ 2023-10-19 10:32 ` Kundanala, Praveen Teja
2023-10-20 7:23 ` Michal Simek
0 siblings, 1 reply; 11+ messages in thread
From: Kundanala, Praveen Teja @ 2023-10-19 10:32 UTC (permalink / raw)
To: Krzysztof Kozlowski, srinivas.kandagatla, robh+dt,
krzysztof.kozlowski+dt, conor+dt, Simek, Michal, devicetree,
linux-arm-kernel
Cc: linux-kernel
[AMD Official Use Only - General]
Hi Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Thursday, October 19, 2023 2:58 PM
> To: Kundanala, Praveen Teja <praveen.teja.kundanala@amd.com>;
> srinivas.kandagatla@linaro.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; Simek, Michal
> <michal.simek@amd.com>; Kundanala, Praveen Teja
> <praveen.teja.kundanala@amd.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Subject: Re: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
> > Add nvmem DT nodes for ZynqMP SOC
> >
> > Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> > ---
> > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59
> > +++++++++++++++++++++++++-
> > 1 file changed, 57 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > index b61fc99cd911..b7433e6b9d6c 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > @@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
> > mbox-names = "tx", "rx";
> > };
> >
> > - nvmem_firmware {
> > + nvmem-firmware {
>
> Node names should be generic. See also an explanation and list of examples
> (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-
> basics.html#generic-names-recommendation
[Kundanala, Praveen Teja] Okay
>
>
> > compatible = "xlnx,zynqmp-nvmem-fw";
>
> It does not look like you tested the DTS against bindings. Please run `make
> dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst
> or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-
> sources-with-the-devicetree-schema/
> for instructions).
[Kundanala, Praveen Teja] Missed it, Will run and send V3.
>
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > - soc_revision: soc_revision@0 {
> > + soc_revision: soc-revision@0 {
> > reg = <0x0 0x4>;
> > };
>
> Wasn't this fixed already by Michal?
[Kundanala, Praveen Teja] Took base on Srinivas for-next repo and Michal's changes were not reflected in that repo.
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
2023-10-19 10:32 ` Kundanala, Praveen Teja
@ 2023-10-20 7:23 ` Michal Simek
0 siblings, 0 replies; 11+ messages in thread
From: Michal Simek @ 2023-10-20 7:23 UTC (permalink / raw)
To: Kundanala, Praveen Teja, Krzysztof Kozlowski,
srinivas.kandagatla, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree, linux-arm-kernel
Cc: linux-kernel
Hi,
On 10/19/23 12:32, Kundanala, Praveen Teja wrote:
> [AMD Official Use Only - General]
>
> Hi Kozlowski,
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Thursday, October 19, 2023 2:58 PM
>> To: Kundanala, Praveen Teja <praveen.teja.kundanala@amd.com>;
>> srinivas.kandagatla@linaro.org; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; Simek, Michal
>> <michal.simek@amd.com>; Kundanala, Praveen Teja
>> <praveen.teja.kundanala@amd.com>; devicetree@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
>>
>> Caution: This message originated from an External Source. Use proper caution
>> when opening attachments, clicking links, or responding.
>>
>>
>> On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
>>> Add nvmem DT nodes for ZynqMP SOC
>>>
>>> Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
>>> ---
>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59
>>> +++++++++++++++++++++++++-
>>> 1 file changed, 57 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> index b61fc99cd911..b7433e6b9d6c 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> @@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
>>> mbox-names = "tx", "rx";
>>> };
>>>
>>> - nvmem_firmware {
>>> + nvmem-firmware {
>>
>> Node names should be generic. See also an explanation and list of examples
>> (not exhaustive) in DT specification:
>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-
>> basics.html#generic-names-recommendation
> [Kundanala, Praveen Teja] Okay
>>
>>
>>> compatible = "xlnx,zynqmp-nvmem-fw";
>>
>> It does not look like you tested the DTS against bindings. Please run `make
>> dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst
>> or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-
>> sources-with-the-devicetree-schema/
>> for instructions).
> [Kundanala, Praveen Teja] Missed it, Will run and send V3.
>>
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>>
>>> - soc_revision: soc_revision@0 {
>>> + soc_revision: soc-revision@0 {
>>> reg = <0x0 0x4>;
>>> };
>>
>> Wasn't this fixed already by Michal?
> [Kundanala, Praveen Teja] Took base on Srinivas for-next repo and Michal's changes were not reflected in that repo.
Feel free to drop this from series that it can go via nvmem tree directly.
And when this is merged we can add just this patch via my tree.
Thanks,
Michal
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V2 4/5] nvmem: zynqmp_nvmem: Add support to access efuse
2023-10-19 6:06 [PATCH V2 0/5] Add ZynqMP efuse access support Praveen Teja Kundanala
` (2 preceding siblings ...)
2023-10-19 6:06 ` [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes Praveen Teja Kundanala
@ 2023-10-19 6:06 ` Praveen Teja Kundanala
2023-10-19 6:06 ` [PATCH V2 5/5] MAINTAINERS: Add maintainers for ZynqMP NVMEM driver Praveen Teja Kundanala
4 siblings, 0 replies; 11+ messages in thread
From: Praveen Teja Kundanala @ 2023-10-19 6:06 UTC (permalink / raw)
To: srinivas.kandagatla, robh+dt, krzysztof.kozlowski+dt, conor+dt,
michal.simek, praveent, devicetree, linux-arm-kernel
Cc: linux-kernel
Add support to read/write efuse memory map of ZynqMP
Below are the offsets of ZynqMP efuse memory map
0 - SOC version(read only)
0xC - 0xFC -ZynqMP specific purpose efuses
0x100 - 0x17F - Physical Unclonable Function(PUF)
efuses repurposed as user efuses
Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
---
drivers/nvmem/zynqmp_nvmem.c | 218 ++++++++++++++++++++++++++++++-----
1 file changed, 186 insertions(+), 32 deletions(-)
diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c
index 7f15aa89a9d0..a3bb8c3a831b 100644
--- a/drivers/nvmem/zynqmp_nvmem.c
+++ b/drivers/nvmem/zynqmp_nvmem.c
@@ -1,8 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Xilinx, Inc.
+ * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc.
*/
+#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
@@ -10,36 +12,190 @@
#include <linux/firmware/xlnx-zynqmp.h>
#define SILICON_REVISION_MASK 0xF
+#define P_USER_0_64_UPPER_MASK GENMASK(31, 16)
+#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
+#define WORD_INBYTES 4
+#define SOC_VER_SIZE 0x4
+#define EFUSE_MEMORY_SIZE 0x177
+#define UNUSED_SPACE 0x8
+#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \
+ EFUSE_MEMORY_SIZE)
+#define SOC_VERSION_OFFSET 0x0
+#define EFUSE_START_OFFSET 0xC
+#define EFUSE_END_OFFSET 0xFC
+#define EFUSE_PUF_START_OFFSET 0x100
+#define EFUSE_PUF_MID_OFFSET 0x140
+#define EFUSE_PUF_END_OFFSET 0x17F
+#define EFUSE_NOT_ENABLED 29
-struct zynqmp_nvmem_data {
- struct device *dev;
- struct nvmem_device *nvmem;
+/*
+ * efuse access type
+ */
+enum efuse_access {
+ EFUSE_READ = 0,
+ EFUSE_WRITE
+};
+
+/**
+ * struct xilinx_efuse - the basic structure
+ * @src: address of the buffer to store the data to be write/read
+ * @size: read/write word count
+ * @offset: read/write offset
+ * @flag: 0 - represents efuse read and 1- represents efuse write
+ * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
+ * 1 - represents puf user fuse row number.
+ *
+ * this structure stores all the required details to
+ * read/write efuse memory.
+ */
+struct xilinx_efuse {
+ u64 src;
+ u32 size;
+ u32 offset;
+ enum efuse_access flag;
+ u32 pufuserfuse;
};
-static int zynqmp_nvmem_read(void *context, unsigned int offset,
- void *val, size_t bytes)
+static int zynqmp_efuse_access(void *context, unsigned int offset,
+ void *val, size_t bytes, enum efuse_access flag,
+ unsigned int pufflag)
{
+ struct device *dev = context;
+ struct xilinx_efuse *efuse;
+ dma_addr_t dma_addr;
+ dma_addr_t dma_buf;
+ size_t words = bytes / WORD_INBYTES;
int ret;
- int idcode, version;
- struct zynqmp_nvmem_data *priv = context;
-
- ret = zynqmp_pm_get_chipid(&idcode, &version);
- if (ret < 0)
- return ret;
+ int value;
+ char *data;
+
+ if (bytes % WORD_INBYTES != 0) {
+ dev_err(dev, "Bytes requested should be word aligned\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (pufflag == 0 && offset % WORD_INBYTES) {
+ dev_err(dev, "Offset requested should be word aligned\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (pufflag == 1 && flag == EFUSE_WRITE) {
+ memcpy(&value, val, bytes);
+ if ((offset == EFUSE_PUF_START_OFFSET ||
+ offset == EFUSE_PUF_MID_OFFSET) &&
+ value & P_USER_0_64_UPPER_MASK) {
+ dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (offset == EFUSE_PUF_END_OFFSET &&
+ (value & P_USER_127_LOWER_4_BIT_MASK)) {
+ dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n");
+ return -EOPNOTSUPP;
+ }
+ }
+
+ efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
+ &dma_addr, GFP_KERNEL);
+ if (!efuse)
+ return -ENOMEM;
- dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
- *(int *)val = version & SILICON_REVISION_MASK;
+ data = dma_alloc_coherent(dev, sizeof(bytes),
+ &dma_buf, GFP_KERNEL);
+ if (!data) {
+ ret = -ENOMEM;
+ goto efuse_data_fail;
+ }
+
+ if (flag == EFUSE_WRITE) {
+ memcpy(data, val, bytes);
+ efuse->flag = EFUSE_WRITE;
+ } else {
+ efuse->flag = EFUSE_READ;
+ }
+
+ efuse->src = dma_buf;
+ efuse->size = words;
+ efuse->offset = offset;
+ efuse->pufuserfuse = pufflag;
+
+ zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
+ if (ret != 0) {
+ if (ret == EFUSE_NOT_ENABLED) {
+ dev_err(dev, "efuse access is not enabled\n");
+ ret = -EOPNOTSUPP;
+ } else {
+ dev_err(dev, "Error in efuse read %x\n", ret);
+ ret = -EPERM;
+ }
+ goto efuse_access_err;
+ }
+
+ if (flag == EFUSE_READ)
+ memcpy(val, data, bytes);
+efuse_access_err:
+ dma_free_coherent(dev, sizeof(bytes),
+ data, dma_buf);
+efuse_data_fail:
+ dma_free_coherent(dev, sizeof(struct xilinx_efuse),
+ efuse, dma_addr);
+
+ return ret;
+}
- return 0;
+static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes)
+{
+ struct device *dev = context;
+ int ret;
+ int pufflag = 0;
+ int idcode;
+ int version;
+
+ if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
+ pufflag = 1;
+
+ switch (offset) {
+ /* Soc version offset is zero */
+ case SOC_VERSION_OFFSET:
+ if (bytes != SOC_VER_SIZE)
+ return -EOPNOTSUPP;
+
+ ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version);
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
+ *(int *)val = version & SILICON_REVISION_MASK;
+ break;
+ /* Efuse offset starts from 0xc */
+ case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
+ case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
+ ret = zynqmp_efuse_access(context, offset, val,
+ bytes, EFUSE_READ, pufflag);
+ break;
+ default:
+ *(u32 *)val = 0xDEADBEEF;
+ ret = 0;
+ break;
+ }
+
+ return ret;
}
-static struct nvmem_config econfig = {
- .name = "zynqmp-nvmem",
- .owner = THIS_MODULE,
- .word_size = 1,
- .size = 1,
- .read_only = true,
-};
+static int zynqmp_nvmem_write(void *context,
+ unsigned int offset, void *val, size_t bytes)
+{
+ int pufflag = 0;
+
+ if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
+ return -EOPNOTSUPP;
+
+ if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
+ pufflag = 1;
+
+ return zynqmp_efuse_access(context, offset,
+ val, bytes, EFUSE_WRITE, pufflag);
+}
static const struct of_device_id zynqmp_nvmem_match[] = {
{ .compatible = "xlnx,zynqmp-nvmem-fw", },
@@ -50,21 +206,19 @@ MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
static int zynqmp_nvmem_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct zynqmp_nvmem_data *priv;
-
- priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
+ struct nvmem_config econfig = {};
- priv->dev = dev;
+ econfig.name = "zynqmp-nvmem";
+ econfig.owner = THIS_MODULE;
+ econfig.word_size = 1;
+ econfig.size = ZYNQMP_NVMEM_SIZE;
econfig.dev = dev;
econfig.add_legacy_fixed_of_cells = true;
+ econfig.priv = dev;
econfig.reg_read = zynqmp_nvmem_read;
- econfig.priv = priv;
-
- priv->nvmem = devm_nvmem_register(dev, &econfig);
+ econfig.reg_write = zynqmp_nvmem_write;
- return PTR_ERR_OR_ZERO(priv->nvmem);
+ return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
}
static struct platform_driver zynqmp_nvmem_driver = {
@@ -77,6 +231,6 @@ static struct platform_driver zynqmp_nvmem_driver = {
module_platform_driver(zynqmp_nvmem_driver);
-MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>, Nava kishore Manne <nava.kishore.manne@amd.com>");
+MODULE_AUTHOR("Kalyani Akula <kalyani.akula@amd.com>, Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>");
MODULE_DESCRIPTION("ZynqMP NVMEM driver");
MODULE_LICENSE("GPL");
--
2.36.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH V2 5/5] MAINTAINERS: Add maintainers for ZynqMP NVMEM driver
2023-10-19 6:06 [PATCH V2 0/5] Add ZynqMP efuse access support Praveen Teja Kundanala
` (3 preceding siblings ...)
2023-10-19 6:06 ` [PATCH V2 4/5] nvmem: zynqmp_nvmem: Add support to access efuse Praveen Teja Kundanala
@ 2023-10-19 6:06 ` Praveen Teja Kundanala
4 siblings, 0 replies; 11+ messages in thread
From: Praveen Teja Kundanala @ 2023-10-19 6:06 UTC (permalink / raw)
To: srinivas.kandagatla, robh+dt, krzysztof.kozlowski+dt, conor+dt,
michal.simek, praveent, devicetree, linux-arm-kernel
Cc: linux-kernel
Add maintainers for ZynqMP NVMEM driver and driver document.
Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..c3370a8a7709 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23765,6 +23765,14 @@ M: Harsha <harsha.harsha@amd.com>
S: Maintained
F: drivers/crypto/xilinx/zynqmp-sha.c
+XILINX ZYNQMP NVMEM DRIVER
+M: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
+M: Kalyani Akula <kalyani.akula@amd.com>
+R: Michal Simek <michal.simek@amd.com>
+S: Maintained
+F: Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
+F: drivers/nvmem/zynqmp_nvmem.c
+
XILLYBUS DRIVER
M: Eli Billauer <eli.billauer@gmail.com>
L: linux-kernel@vger.kernel.org
--
2.36.1
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