Re: [PATCH v5 2/8] clk: starfive: Add system-0 domain PLL clock driver

[Jerome Brunet <jbrunet@baylibre.com>]

On Sat 03 Oct 2026 at 11:02, Changhuang Liang <changhuang.liang@starfivetech.com> wrote:

>> > +static const struct jhb100_pll_info jhb100_sys0_pll_info[] = {
>> > +	JHB100_PLL(JHB100_SYS0PLL_PLL2_OUT, "pll2_out",
>> jhb100_pll2_presets,
>> > +		   ARRAY_SIZE(jhb100_pll2_presets), JHB100_PLL2_OFFSET, false),
>> > +	_JHB100_PLL(JHB100_SYS0PLL_PLL3_OUT, "pll3_out",
>> jhb100_pll3_presets,
>> > +		    ARRAY_SIZE(jhb100_pll3_presets), JHB100_PLL3_OFFSET,
>> > +		    CLK_IS_CRITICAL, false),
>> > +	_JHB100_PLL(JHB100_SYS0PLL_PLL4_OUT, "pll4_out", NULL, 0,
>> > +		    JHB100_PLL4_OFFSET, CLK_IGNORE_UNUSED, true),
>> 
>> Please comment when adding CLK_IGNORE_UNUSED so people have an idea
>> why it is needed and how it can be removed
>
> OK, I understand that there is an intention to remove this flag. On our SoC, some clocks are 
> typically not referenced by any driver, but we don't want them to be turned off. We currently 
> use CLK_IGNORE_UNUSED to preserve their hardware-default enabled state. Perhaps in the 
> next version we will replace it with CLK_IS_CRITICAL.

CLK_IGNORE_UNUSED and CLK_IS_CRITICAL do not express the same thing both
equally need to be commented so a few years from now, we are not left
wondering why this was added.

You do not have a driver for this clock today. The fact you still *need*
that clock show maybe you should have one and maybe someone, someday,
will fix this.

>
>>