From: Vojtech Pavlik <vojtech@suse.cz>
To: Daniela Engert <dani@ngrt.de>
Cc: Shawn Starr <spstarr@sh0n.net>, Vojtech Pavlik <vojtech@suse.cz>,
LKML <linux-kernel@vger.kernel.org>,
Martin Dalecki <martin@dalecki.de>
Subject: Re: [patch] PIIX rewrite patch, pre-final
Date: Thu, 14 Mar 2002 08:30:38 +0100 [thread overview]
Message-ID: <20020314083038.A31923@ucw.cz> (raw)
In-Reply-To: <20020314075258.A31815@ucw.cz> <20020314061803.EDF56E415@mail.medav.de>
In-Reply-To: <20020314061803.EDF56E415@mail.medav.de>; from dani@ngrt.de on Thu, Mar 14, 2002 at 08:24:02AM +0100
On Thu, Mar 14, 2002 at 08:24:02AM +0100, Daniela Engert wrote:
> On Thu, 14 Mar 2002 07:52:58 +0100, Vojtech Pavlik wrote:
>
> >> This will benifit PIIX3 chipsets? :)
> >It should.
>
> Are you aware of the batches of broken PIIX3 chips ?
I don't know of any IDE-related errata for the PIIX3 chip. At least
Intel didn't publish any and there doesn't seem to be any workarounds in
the original piix.c code, only a statement stating that the PIIX3 UDMA
is broken, however, as far as I know, PIIX3 isn't UDMA capable at all.
(Hmm, perhaps some BIOSes enable UDMA on PIIX3, that'd explain it ...
though I believe that's quite improbable).
In what way are those batches broken?
--
Vojtech Pavlik
SuSE Labs
next prev parent reply other threads:[~2002-03-14 7:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-03-13 23:14 Vojtech Pavlik
2002-03-14 1:04 ` Shawn Starr
2002-03-14 6:52 ` Vojtech Pavlik
2002-03-14 7:24 ` Daniela Engert
2002-03-14 7:30 ` Vojtech Pavlik [this message]
2002-03-14 7:36 ` Andre Hedrick
2002-03-14 7:46 ` Vojtech Pavlik
2002-03-14 7:38 ` Andre Hedrick
2002-03-14 7:44 ` Daniela Engert
2002-03-14 8:18 ` Vojtech Pavlik
2002-03-14 8:23 ` Vojtech Pavlik
2002-03-14 9:48 ` Daniela Engert
2002-03-14 10:14 ` Vojtech Pavlik
2002-03-14 14:19 ` Alan Cox
2002-03-14 14:39 ` Shawn Starr
2002-03-14 16:47 ` Tom Rini
2002-03-14 16:49 ` Vojtech Pavlik
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