Re: [patch] PIIX rewrite patch, pre-final

[Vojtech Pavlik <vojtech@suse.cz>]

On Thu, Mar 14, 2002 at 09:18:08AM +0100, Vojtech Pavlik wrote:
> On Thu, Mar 14, 2002 at 08:44:42AM +0100, Daniela Engert wrote:
> 
> > The PIIX3 bug is real, I have several user reports about it!
> 
> Thanks A LOT for the tables, added are some comments from me ...
> 
> >  Vendor
> >  | Device
> >  | | Revision			       ATA	ATAPI	     ATA66  ATA133
> >  | | | south/host bridge id	     PIO  DMA  PIO  DMA  ATA33 | ATA100|   Docs
> >  | | | | south/host bridge rev.     32bit  |  32bit  |	   |   |   |   |  avail
> >  | | | | |			      |    |	|    |	   |   |   |   |    |
> >  v v v v v			      v    v	v    v	   v   v   v   v    v
> > 
> >  0x8086 Intel
> >    0x1230 PIIX		      x    x	x    x	   -   -   -   -    x
> >      < 02			      x    -	x    -	   -   -   -   -    x
> 
> I suppose this means on PIIXes with rev 00 and 01 of the IDE controller
> DMA transfers don't work reliably, right?
> 
> >        0x84C4 Orion
> > 	 < 04			      x    -	x    -	   -   -   -   -    x
> 
> And this means that if there is an 84c4 PCI bridge in the system with
> rev less than 04 (04 is OK), then DMA transfers are broken again.

And there is one more Intel chip:

0x1234, the infamous MPIIX. Can do PIO only, 32 bit is OK, has a single
channel switchable to primary or secondary, IDETIM is located in
registers 6C-6D on the ISA bridge. Docs available.

-- 
Vojtech Pavlik
SuSE Labs