From: Vojtech Pavlik <vojtech@suse.cz>
To: Daniela Engert <dani@ngrt.de>
Cc: Vojtech Pavlik <vojtech@suse.cz>,
LKML <linux-kernel@vger.kernel.org>,
Martin Dalecki <martin@dalecki.de>,
Shawn Starr <spstarr@sh0n.net>
Subject: Re: [patch] PIIX rewrite patch, pre-final
Date: Thu, 14 Mar 2002 11:14:16 +0100 [thread overview]
Message-ID: <20020314111416.A5613@ucw.cz> (raw)
In-Reply-To: <20020314091808.B31998@ucw.cz> <20020314084211.2611E5246@mail.medav.de>
In-Reply-To: <20020314084211.2611E5246@mail.medav.de>; from dani@ngrt.de on Thu, Mar 14, 2002 at 10:48:10AM +0100
On Thu, Mar 14, 2002 at 10:48:10AM +0100, Daniela Engert wrote:
> >00..1f 586
> >20..2f 586a
> >30..3f 586b
> >40..46 586b 3040 silicon
> >Has a bug where the preq# til ddack# bit must be cleared or can cause
> >spontaneous reboots.
> >47..4f 586b 3041 silicon
>
> True. I leave this particular setup to the BIOS which is supposed to
> take care of such idiosyncrasies...
Unfortunately not all BIOSes do. I have at least two reported buggy
BIOSES which set the bit even on the 3040 silicon.
> >> 0x3109 VT8233c x x x x x x x - -
> >> 0x3147 VT8233a x x x x x x x x -
> >>
> >> known bugs:
> >> - all: no host side cable type detection.
> >
> >Not true, for the UDMA100 and UDMA133 capable ones, there are defined
> >bits in the UDMA_TIMING register. Not all BIOSes use those, though.
>
> Interesting. None of the user reports ever indicated that.
It's possible the BIOSes don't set the bits. My driver also checks if
the BIOS enabled UDMA >= 44MB/s on these chips, assuming 80 cable as
well.
Anyway, the docs state the bits should reflect the cable presence.
> >> --------------------------------------------------------------------------------
> >> 0x10DE Nvidia
> >> 0x01BC nForce x x x x x x x - -
> >>
> >> known bugs:
> >> - nForce: no host side cable type detection.
> >
> >Do you have any info on this one? I'd really like to have a Linux driver
> >for it ...
>
> I have no docs, but my father's machine has this chip built in :-) My
> driver is running it just fine. In fact, this is a clone of the ATA/100
> capable AMD IDE chip cell with all config register addresses shifted up
> by 0x10.
Thanks for this info. :) I think I'll add the support to my AMD driver.
Could you by any chance send me a PCI config space dump of the IDE
controller there?
> I'm looking forward to the new ATI chipset, let's bet where their IDE
> cell is licenced from :-)
I don't think it'll be Intel. I bet on VIA ...
--
Vojtech Pavlik
SuSE Labs
next prev parent reply other threads:[~2002-03-14 10:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-03-13 23:14 Vojtech Pavlik
2002-03-14 1:04 ` Shawn Starr
2002-03-14 6:52 ` Vojtech Pavlik
2002-03-14 7:24 ` Daniela Engert
2002-03-14 7:30 ` Vojtech Pavlik
2002-03-14 7:36 ` Andre Hedrick
2002-03-14 7:46 ` Vojtech Pavlik
2002-03-14 7:38 ` Andre Hedrick
2002-03-14 7:44 ` Daniela Engert
2002-03-14 8:18 ` Vojtech Pavlik
2002-03-14 8:23 ` Vojtech Pavlik
2002-03-14 9:48 ` Daniela Engert
2002-03-14 10:14 ` Vojtech Pavlik [this message]
2002-03-14 14:19 ` Alan Cox
2002-03-14 14:39 ` Shawn Starr
2002-03-14 16:47 ` Tom Rini
2002-03-14 16:49 ` Vojtech Pavlik
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