Enabling L2 cache for overdrive CPUs.

Enabling L2 cache for overdrive CPUs.

[davej]

Some CPU overdrives (such as those made by powerleap) mean
that we get a CPU with L2 cache disabled by default, and
a BIOS that doesn't know how to turn it on.
The patch below is untested, and I'd like some feedback
from folks (preferably those with these wacky overdrives,
but also from regular intel CPUs too - disable L2 in your
bios and try booting with 'enable-l2' and see what happens).

    Dave

diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/intel.c linux-2.5/arch/i386/kernel/cpu/intel.c
--- bk-linus/arch/i386/kernel/cpu/intel.c	2003-02-25 13:10:08.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/intel.c	2003-02-25 13:07:52.000000000 -0100
@@ -8,6 +8,7 @@
 #include <asm/processor.h>
 #include <asm/msr.h>
 #include <asm/uaccess.h>
+#include <asm/system.h>
 
 #include "cpu.h"
 
@@ -75,6 +76,36 @@ static int __init P4_disable_ht(char *s)
 }
 __setup("noht", P4_disable_ht);
 
+/*
+ * Some 'overdrive' boards, such as those from Powerleap don't have
+ * the L2 cache enabled, and the BIOS doesn't know about it, so we
+ * have this option to 'force' it on.
+ */
+static int __init P2_enable_L2(char *s)
+{
+	unsigned long cr0, lo, hi;
+
+	printk ("CPU: Enabling L2 cache.\n");
+
+	__asm__ ("cli");
+
+	cr0 = read_cr0();
+	cr0 |= 1<<30;
+	write_cr0 (cr0);
+
+	rdmsr (0x11e, lo, hi);
+	lo |= 0x40101;
+	wrmsr (0x11e, lo, hi);
+
+	cr0 &= ~(1<<30);
+	write_cr0 (cr0);
+
+	wbinvd();
+	__asm__("sti");
+	return 0;
+}
+__setup("enable-l2", P2_enable_L2);
+
 #define LVL_1_INST	1
 #define LVL_1_DATA	2
 #define LVL_2		3

Re: Enabling L2 cache for overdrive CPUs.

[Mikael Pettersson]

davej@codemonkey.org.uk writes:
 > Some CPU overdrives (such as those made by powerleap) mean
 > that we get a CPU with L2 cache disabled by default, and
 > a BIOS that doesn't know how to turn it on.
 > The patch below is untested, and I'd like some feedback
 > from folks (preferably those with these wacky overdrives,
 > but also from regular intel CPUs too - disable L2 in your
 > bios and try booting with 'enable-l2' and see what happens).
...
 > +	cr0 = read_cr0();
 > +	cr0 |= 1<<30;
 > +	write_cr0 (cr0);
 > +
 > +	rdmsr (0x11e, lo, hi);
 > +	lo |= 0x40101;
 > +	wrmsr (0x11e, lo, hi);
 > +
 > +	cr0 &= ~(1<<30);
 > +	write_cr0 (cr0);
 > +
 > +	wbinvd();

Ugh. Is this for the PII overdrive for PPro socket or what?

Seems awfully dangerous to have a __setup() clobber MSRs without
checking the cpuid first. 
Shouldn't this be in the CPU detection/quirks code instead?
It already contains stuff similar to this.

/Mikael

Re: Enabling L2 cache for overdrive CPUs.

[Dave Jones]

On Wed, Feb 26, 2003 at 03:26:27PM +0100, Mikael Pettersson wrote:

 > Ugh. Is this for the PII overdrive for PPro socket or what?

Celerons iirc. I got a mail from someone annoyed at the
binary only module that powerleap gave him to do this.
I just disassembled it and turned it back to C.

 > Seems awfully dangerous to have a __setup() clobber MSRs without
 > checking the cpuid first. 
 > Shouldn't this be in the CPU detection/quirks code instead?
 > It already contains stuff similar to this.

That is another option that could be done, yes..

        Dave