[PATCH 1/1] pci: Add Citrine quirk

[PATCH 1/1] pci: Add Citrine quirk

[brking]

The IBM Citrine chipset has a feature that if PCI config register
0xA0 is read while DMAs are being performed to it, there is the possiblity
that the parity will be wrong on the PCI bus, causing a parity error and
a master abort. On this chipset, this register is simply a debug register
for the chip developers and the registers after it are not defined.
Patch sets cfg_size to 0xA0 to prevent this problem from being seen.

Signed-off-by: Brian King <brking@us.ibm.com>
---

 linux-2.6.11-rc2-bk5-bjking1/drivers/pci/quirks.c |   10 ++++++++++
 1 files changed, 10 insertions(+)

diff -puN drivers/pci/quirks.c~pci_citrine_quirk drivers/pci/quirks.c
--- linux-2.6.11-rc2-bk5/drivers/pci/quirks.c~pci_citrine_quirk	2005-01-27 16:51:28.000000000 -0600
+++ linux-2.6.11-rc2-bk5-bjking1/drivers/pci/quirks.c	2005-01-27 16:51:28.000000000 -0600
@@ -216,6 +216,16 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_2, 	quirk_natoma );
 
 /*
+ *  This chip can cause PCI parity errors if config register 0xA0 is read
+ *  while DMAs are occurring.
+ */
+static void __devinit quirk_citrine(struct pci_dev *dev)
+{
+	dev->cfg_size = 0xA0;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine );
+
+/*
  *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
  *  If it's needed, re-allocate the region.
  */
_

IBM SerialRAID

[shogunx]

Hi all,

Has anyone successfully inplemented an IBM SerialRAID card under the linux
kernel?  I know we have no code for it as of 2.6.10, but I figured that
someone may have a patched together module floating around somewhere.
These are typically used in pSeries and eSeries machines as (surprise) as
raid controller for SSA disk arrays.

Thanks in advance,
Scott

sleekfreak pirate broadcast
http://sleekfreak.ath.cx:81/

Re: [PATCH 1/1] pci: Add Citrine quirk

[Greg KH]

On Fri, Jan 28, 2005 at 08:53:47AM -0600, brking@us.ibm.com wrote:
> 
> The IBM Citrine chipset has a feature that if PCI config register
> 0xA0 is read while DMAs are being performed to it, there is the possiblity
> that the parity will be wrong on the PCI bus, causing a parity error and
> a master abort. On this chipset, this register is simply a debug register
> for the chip developers and the registers after it are not defined.
> Patch sets cfg_size to 0xA0 to prevent this problem from being seen.
> 
> Signed-off-by: Brian King <brking@us.ibm.com>

Applied, thanks.

greg k-h