Re: perfmon2 merge news

[Stephane Eranian <eranian@hpl.hp.com>]

Will,

On Fri, Nov 16, 2007 at 12:13:07PM -0500, William Cohen wrote:
> Andi Kleen wrote:
> >On Fri, Nov 16, 2007 at 08:00:56AM -0800, Stephane Eranian wrote:
> >>No, he is talking about something similar to what was in perfctr.
> >>The kernel emulates 64-bit counters in software and that is you
> >>get back when you read the counters. If you read via RDPMC, you
> >>get 40 bits. To reconstruct the full 64-bit value from user land
> >>you need the upper bits. One approach is for the kernel to allow
> >>you to remap a page that has the 64-bit (software) counters. With
> >>that and a bit of mask/shifting you can reconstruct the full value.
> >
> >You mean the page contains the upper [40;63] bits? 
> >
> >Sounds reasonable, although I don't remember seeing that when I looked
> >at the perfmon code last.
> 
> Upper 32-bit ([32:63]). On many implementations the only lower 32-bit are 
> available in the register. the 32:40 bits in several processor 
> implementation of x86 processors can not be set to bit outside of sign 
> extension of bit 32. On other processor implementations the event counters 
> are only 32-bit in width.
> 
That is quite true on Intel's. Perfmon2 only considers the bottom 31 bits as
true counter bits, the rest is forced to 1. This is true even on Intel Core 2.

--
-Stephane