From: Andi Kleen <ak@suse.de>
To: asit.k.mallick@intel.com, linux-kernel@vger.kernel.org
Subject: [PATCH] [3/20] x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUs
Date: Thu, 3 Jan 2008 01:49:58 +0100 (CET) [thread overview]
Message-ID: <20080103004958.44D3314D40@wotan.suse.de> (raw)
In-Reply-To: <20080103149.088038000@suse.de>
According to Intel RDTSC can be always synchronized with LFENCE
on all current CPUs. Implement the necessary CPUID bit for that.
It is unclear yet if that is true for all future CPUs too,
but if there's another way the kernel can be always updated.
Cc: asit.k.mallick@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
---
arch/x86/kernel/cpu/intel.c | 3 ++-
arch/x86/kernel/setup_64.c | 5 +----
include/asm-x86/cpufeature.h | 1 +
3 files changed, 4 insertions(+), 5 deletions(-)
Index: linux/arch/x86/kernel/setup_64.c
===================================================================
--- linux.orig/arch/x86/kernel/setup_64.c
+++ linux/arch/x86/kernel/setup_64.c
@@ -899,10 +899,7 @@ static void __cpuinit init_intel(struct
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
if (c->x86 == 6)
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
- if (c->x86 == 15)
- set_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
- else
- clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
+ set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
c->x86_max_cores = intel_num_cpu_cores(c);
srat_detect_node();
Index: linux/include/asm-x86/cpufeature.h
===================================================================
--- linux.orig/include/asm-x86/cpufeature.h
+++ linux/include/asm-x86/cpufeature.h
@@ -80,6 +80,7 @@
#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
+#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
Index: linux/arch/x86/kernel/cpu/intel.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/intel.c
+++ linux/arch/x86/kernel/cpu/intel.c
@@ -203,9 +203,10 @@ static void __cpuinit init_intel(struct
}
#endif
+ if (cpu_has_xmm)
+ set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
if (c->x86 == 15) {
set_bit(X86_FEATURE_P4, c->x86_capability);
- set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
}
if (c->x86 == 6)
set_bit(X86_FEATURE_P3, c->x86_capability);
next prev parent reply other threads:[~2008-01-03 0:50 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-03 0:49 [PATCH] [1/20] x86: Make ptrace.h safe to include from assembler code Andi Kleen
2008-01-03 0:49 ` [PATCH] [2/20] x86: Implement support to synchronize RDTSC through MFENCE on AMD CPUs Andi Kleen
2008-01-03 0:49 ` Andi Kleen [this message]
2008-01-03 0:49 ` [PATCH] [4/20] x86: Move nop declarations into separate include file Andi Kleen
2008-01-03 0:50 ` [PATCH] [5/20] x86: Introduce nsec_barrier() Andi Kleen
2008-01-03 10:47 ` Ingo Molnar
2008-01-03 12:55 ` Andi Kleen
2008-01-07 20:01 ` [PATCH] [5/20] x86: Introduce nsec_barrier() II Andi Kleen
2008-01-03 0:50 ` [PATCH] [6/20] x86: Remove get_cycles_sync Andi Kleen
2008-01-03 0:50 ` [PATCH] [7/20] x86: Remove the now unused X86_FEATURE_SYNC_RDTSC Andi Kleen
2008-01-03 0:50 ` [PATCH] [8/20] x86: Make TIF_MCE_NOTIFY optional Andi Kleen
2008-01-03 0:50 ` [PATCH] [9/20] x86: Don't use oops_begin in 64bit mce code Andi Kleen
2008-01-03 10:39 ` Ingo Molnar
2008-01-03 12:52 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [10/20] i386: Move MWAIT idle check to generic CPU initialization Andi Kleen
2008-01-03 10:42 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [11/20] x86: Use the correct cpuid method to detect MWAIT support for C states Andi Kleen
2008-01-03 10:45 ` Ingo Molnar
2008-01-03 12:53 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [12/20] x86: Use a per cpu timer for correctable machine check checking Andi Kleen
2008-01-03 10:49 ` Ingo Molnar
2008-01-03 12:56 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [13/20] x86: Use a deferrable timer for the correctable machine check poller Andi Kleen
2008-01-03 0:50 ` [PATCH] [14/20] x86: Add per cpu counters for machine check polls / machine check events Andi Kleen
2008-01-03 0:50 ` [PATCH] [15/20] x86: Move X86_FEATURE_CONSTANT_TSC into early cpu feature detection Andi Kleen
2008-01-03 11:03 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [16/20] x86: Allow TSC clock source on AMD Fam10h and some cleanup Andi Kleen
2008-01-04 8:38 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [17/20] x86: Remove explicit C3 TSC check on 64bit Andi Kleen
2008-01-04 8:38 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h Andi Kleen
2008-01-04 8:40 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [19/20] x86: Use shorter addresses in i386 segfault printks Andi Kleen
2008-01-03 10:56 ` Ingo Molnar
2008-01-03 12:56 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [20/20] x86: Print which shared library/executable faulted in segfault etc. messages Andi Kleen
2008-01-03 6:28 ` Eric Dumazet
2008-01-03 11:00 ` Ingo Molnar
2008-01-03 13:06 ` Andi Kleen
2008-01-03 9:54 ` [PATCH] [1/20] x86: Make ptrace.h safe to include from assembler code Ingo Molnar
2008-01-03 12:57 ` Andi Kleen
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