From: Andi Kleen <ak@suse.de>
To: linux-kernel@vger.kernel.org
Subject: [PATCH] [12/20] x86: Use a per cpu timer for correctable machine check checking
Date: Thu, 3 Jan 2008 01:50:07 +0100 (CET) [thread overview]
Message-ID: <20080103005007.CE13A14D40@wotan.suse.de> (raw)
In-Reply-To: <20080103149.088038000@suse.de>
Previously the code used a single timer that then used smp_call_function
to interrupt all CPUs while the original CPU was waiting for them.
But it is better / more real time and more power friendly to simply run
individual timers on each CPU so they all do this independently.
This way no single CPU has to wait for all others.
Signed-off-by: Andi Kleen <ak@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce_64.c | 68 +++++++++++++++++++++++++-----------
1 file changed, 48 insertions(+), 20 deletions(-)
Index: linux/arch/x86/kernel/cpu/mcheck/mce_64.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ linux/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -363,17 +363,14 @@ void mce_log_therm_throt_event(unsigned
static int check_interval = 5 * 60; /* 5 minutes */
static int next_interval; /* in jiffies */
static void mcheck_timer(struct work_struct *work);
-static DECLARE_DELAYED_WORK(mcheck_work, mcheck_timer);
+static DEFINE_PER_CPU(struct delayed_work, mcheck_work);
-static void mcheck_check_cpu(void *info)
+static void mcheck_timer(struct work_struct *work)
{
+ int cpu;
+
if (mce_available(¤t_cpu_data))
do_machine_check(NULL, 0);
-}
-
-static void mcheck_timer(struct work_struct *work)
-{
- on_each_cpu(mcheck_check_cpu, NULL, 1, 1);
/*
* Alert userspace if needed. If we logged an MCE, reduce the
@@ -386,7 +383,8 @@ static void mcheck_timer(struct work_str
(int)round_jiffies_relative(check_interval*HZ));
}
- schedule_delayed_work(&mcheck_work, next_interval);
+ cpu = smp_processor_id();
+ schedule_delayed_work_on(cpu, &per_cpu(mcheck_work, cpu), next_interval);
}
/*
@@ -436,12 +434,44 @@ static struct notifier_block mce_idle_no
};
#endif
+static void mce_timers(int restart)
+{
+ int i;
+ next_interval = restart ? check_interval * HZ : 0;
+ for_each_online_cpu (i) {
+ struct delayed_work *w = &per_cpu(mcheck_work, i);
+ cancel_delayed_work_sync(w);
+ if (restart)
+ schedule_delayed_work_on(i, w,
+ round_jiffies_relative(next_interval));
+ }
+}
+
+static int __cpuinit
+mce_periodic_cpu_cb(struct notifier_block *b, unsigned long action, void *arg)
+{
+ long cpu = (long)arg;
+ struct delayed_work *w = &per_cpu(mcheck_work, cpu);
+ switch (action) {
+ case CPU_DOWN_PREPARE:
+ cancel_delayed_work_sync(w);
+ break;
+ case CPU_ONLINE:
+ case CPU_DOWN_FAILED:
+ schedule_delayed_work_on(cpu, w, next_interval);
+ break;
+ }
+ return NOTIFY_DONE;
+}
+
static __init int periodic_mcheck_init(void)
{
- next_interval = check_interval * HZ;
- if (next_interval)
- schedule_delayed_work(&mcheck_work,
- round_jiffies_relative(next_interval));
+ /* RED-PEN: race here with CPU getting added in parallel. But
+ * if the hotplug lock is aquired here we run into lock ordering
+ * problems with the scheduler code.
+ */
+ hotcpu_notifier(mce_periodic_cpu_cb, 0);
+ mce_timers(1);
#ifdef CONFIG_MCE_NOTIFY
idle_notifier_register(&mce_idle_notifier);
#endif
@@ -520,12 +550,15 @@ static void __cpuinit mce_cpu_features(s
*/
void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
{
+ int cpu = smp_processor_id();
static cpumask_t mce_cpus = CPU_MASK_NONE;
+ INIT_DELAYED_WORK(&per_cpu(mcheck_work, cpu), mcheck_timer);
+
mce_cpu_quirks(c);
if (mce_dont_init ||
- cpu_test_and_set(smp_processor_id(), mce_cpus) ||
+ cpu_test_and_set(cpu, mce_cpus) ||
!mce_available(c))
return;
@@ -751,14 +784,9 @@ static int mce_resume(struct sys_device
/* Reinit MCEs after user configuration changes */
static void mce_restart(void)
{
- if (next_interval)
- cancel_delayed_work(&mcheck_work);
- /* Timer race is harmless here */
+ mce_timers(0);
on_each_cpu(mce_init, NULL, 1, 1);
- next_interval = check_interval * HZ;
- if (next_interval)
- schedule_delayed_work(&mcheck_work,
- round_jiffies_relative(next_interval));
+ mce_timers(1);
}
static struct sysdev_class mce_sysclass = {
next prev parent reply other threads:[~2008-01-03 0:53 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-03 0:49 [PATCH] [1/20] x86: Make ptrace.h safe to include from assembler code Andi Kleen
2008-01-03 0:49 ` [PATCH] [2/20] x86: Implement support to synchronize RDTSC through MFENCE on AMD CPUs Andi Kleen
2008-01-03 0:49 ` [PATCH] [3/20] x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUs Andi Kleen
2008-01-03 0:49 ` [PATCH] [4/20] x86: Move nop declarations into separate include file Andi Kleen
2008-01-03 0:50 ` [PATCH] [5/20] x86: Introduce nsec_barrier() Andi Kleen
2008-01-03 10:47 ` Ingo Molnar
2008-01-03 12:55 ` Andi Kleen
2008-01-07 20:01 ` [PATCH] [5/20] x86: Introduce nsec_barrier() II Andi Kleen
2008-01-03 0:50 ` [PATCH] [6/20] x86: Remove get_cycles_sync Andi Kleen
2008-01-03 0:50 ` [PATCH] [7/20] x86: Remove the now unused X86_FEATURE_SYNC_RDTSC Andi Kleen
2008-01-03 0:50 ` [PATCH] [8/20] x86: Make TIF_MCE_NOTIFY optional Andi Kleen
2008-01-03 0:50 ` [PATCH] [9/20] x86: Don't use oops_begin in 64bit mce code Andi Kleen
2008-01-03 10:39 ` Ingo Molnar
2008-01-03 12:52 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [10/20] i386: Move MWAIT idle check to generic CPU initialization Andi Kleen
2008-01-03 10:42 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [11/20] x86: Use the correct cpuid method to detect MWAIT support for C states Andi Kleen
2008-01-03 10:45 ` Ingo Molnar
2008-01-03 12:53 ` Andi Kleen
2008-01-03 0:50 ` Andi Kleen [this message]
2008-01-03 10:49 ` [PATCH] [12/20] x86: Use a per cpu timer for correctable machine check checking Ingo Molnar
2008-01-03 12:56 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [13/20] x86: Use a deferrable timer for the correctable machine check poller Andi Kleen
2008-01-03 0:50 ` [PATCH] [14/20] x86: Add per cpu counters for machine check polls / machine check events Andi Kleen
2008-01-03 0:50 ` [PATCH] [15/20] x86: Move X86_FEATURE_CONSTANT_TSC into early cpu feature detection Andi Kleen
2008-01-03 11:03 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [16/20] x86: Allow TSC clock source on AMD Fam10h and some cleanup Andi Kleen
2008-01-04 8:38 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [17/20] x86: Remove explicit C3 TSC check on 64bit Andi Kleen
2008-01-04 8:38 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h Andi Kleen
2008-01-04 8:40 ` Ingo Molnar
2008-01-03 0:50 ` [PATCH] [19/20] x86: Use shorter addresses in i386 segfault printks Andi Kleen
2008-01-03 10:56 ` Ingo Molnar
2008-01-03 12:56 ` Andi Kleen
2008-01-03 0:50 ` [PATCH] [20/20] x86: Print which shared library/executable faulted in segfault etc. messages Andi Kleen
2008-01-03 6:28 ` Eric Dumazet
2008-01-03 11:00 ` Ingo Molnar
2008-01-03 13:06 ` Andi Kleen
2008-01-03 9:54 ` [PATCH] [1/20] x86: Make ptrace.h safe to include from assembler code Ingo Molnar
2008-01-03 12:57 ` Andi Kleen
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