* [PATCH] audio: tlv320aic26: fix PLL register configuration
@ 2011-04-28 21:32 Michael Williamson
2011-04-28 21:56 ` Mark Brown
0 siblings, 1 reply; 3+ messages in thread
From: Michael Williamson @ 2011-04-28 21:32 UTC (permalink / raw)
To: alsa-devel; +Cc: linux-kernel, broonie, lrg, tiwai, Michael Williamson
The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS
API for the calculation.
Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.
Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
---
Against 2f666bcf757cb72549f360ef6da02f03620a48b6 of Linus' tree.
I'm not sure if I have this on all the right lists / CC's. get_maintainer.pl
generated a *pile* of addresses...
sound/soc/codecs/tlv320aic26.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c
index e2a7608..51e060b 100644
--- a/sound/soc/codecs/tlv320aic26.c
+++ b/sound/soc/codecs/tlv320aic26.c
@@ -163,8 +163,10 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
/* Configure PLL */
pval = 1;
- jval = (fsref == 44100) ? 7 : 8;
- dval = (fsref == 44100) ? 5264 : 1920;
+ jval = fsref / (aic26->mclk / 2048);
+ dval = fsref - jval * (aic26->mclk / 2048);
+ dval = 10000 * dval / (aic26->mclk / 2048);
+ dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);
qval = 0;
reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);
--
1.7.0.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] audio: tlv320aic26: fix PLL register configuration
2011-04-28 21:32 [PATCH] audio: tlv320aic26: fix PLL register configuration Michael Williamson
@ 2011-04-28 21:56 ` Mark Brown
2011-04-28 22:17 ` Mike Williamson
0 siblings, 1 reply; 3+ messages in thread
From: Mark Brown @ 2011-04-28 21:56 UTC (permalink / raw)
To: Michael Williamson; +Cc: alsa-devel, linux-kernel, lrg, tiwai
On Thu, Apr 28, 2011 at 05:32:57PM -0400, Michael Williamson wrote:
> - jval = (fsref == 44100) ? 7 : 8;
> - dval = (fsref == 44100) ? 5264 : 1920;
> + jval = fsref / (aic26->mclk / 2048);
> + dval = fsref - jval * (aic26->mclk / 2048);
I'd like some more brackets on this line, especially given the
similarity with the previous line. Otherwise this looks fine if a bit
magic:
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] audio: tlv320aic26: fix PLL register configuration
2011-04-28 21:56 ` Mark Brown
@ 2011-04-28 22:17 ` Mike Williamson
0 siblings, 0 replies; 3+ messages in thread
From: Mike Williamson @ 2011-04-28 22:17 UTC (permalink / raw)
To: Mark Brown; +Cc: alsa-devel, linux-kernel, lrg, tiwai
On Thu, Apr 28, 2011 at 5:56 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, Apr 28, 2011 at 05:32:57PM -0400, Michael Williamson wrote:
>
>> - jval = (fsref == 44100) ? 7 : 8;
>> - dval = (fsref == 44100) ? 5264 : 1920;
>> + jval = fsref / (aic26->mclk / 2048);
>> + dval = fsref - jval * (aic26->mclk / 2048);
>
> I'd like some more brackets on this line, especially given the
> similarity with the previous line. Otherwise this looks fine if a bit
> magic:
I will add some parens (and comment the magic?) and resubmit with your ack.
Thanks.
>
> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-04-28 22:23 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2011-04-28 21:32 [PATCH] audio: tlv320aic26: fix PLL register configuration Michael Williamson
2011-04-28 21:56 ` Mark Brown
2011-04-28 22:17 ` Mike Williamson
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