* [PATCH] pwm: dt: Fix description of second PWM cell
@ 2012-10-01 6:47 Thierry Reding
2012-10-05 15:24 ` Sascha Hauer
2012-10-07 3:16 ` Shawn Guo
0 siblings, 2 replies; 3+ messages in thread
From: Thierry Reding @ 2012-10-01 6:47 UTC (permalink / raw)
To: linux-kernel
Cc: Shawn Guo, Sascha Hauer, Philipp Zabel,
Benoît Thébaudeau, Stephen Warren
The second cell in the PWM specifier denotes the period in nanoseconds,
not the duty cycle. The latter can be freely configured at runtime and
a PWM with a fixed duty cycle would be rather pointless.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
---
Documentation/devicetree/bindings/pwm/imx-pwm.txt | 2 +-
Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 +-
Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
index 9b9b185..8522bfb 100644
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible: should be "fsl,<soc>-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. The first cell specifies the per-chip index
- of the PWM to use and the second cell is the duty cycle in nanoseconds.
+ of the PWM to use and the second cell is the period in nanoseconds.
- interrupts: The interrupt for the pwm controller
Example:
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
index b16f4a5..d7946be6 100644
--- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible: should be "fsl,imx23-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. The first cell specifies the per-chip index
- of the PWM to use and the second cell is the duty cycle in nanoseconds.
+ of the PWM to use and the second cell is the period in nanoseconds.
- fsl,pwm-number: the number of PWM devices
Example:
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index bbbeedb..01438ec 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -7,7 +7,7 @@ Required properties:
- reg: physical base address and length of the controller's registers
- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
first cell specifies the per-chip index of the PWM to use and the second
- cell is the duty cycle in nanoseconds.
+ cell is the period in nanoseconds.
Example:
--
1.7.12.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] pwm: dt: Fix description of second PWM cell
2012-10-01 6:47 [PATCH] pwm: dt: Fix description of second PWM cell Thierry Reding
@ 2012-10-05 15:24 ` Sascha Hauer
2012-10-07 3:16 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2012-10-05 15:24 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-kernel, Shawn Guo, Philipp Zabel,
Benoît Thébaudeau, Stephen Warren
On Mon, Oct 01, 2012 at 08:47:33AM +0200, Thierry Reding wrote:
> The second cell in the PWM specifier denotes the period in nanoseconds,
> not the duty cycle. The latter can be freely configured at runtime and
> a PWM with a fixed duty cycle would be rather pointless.
>
> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> Documentation/devicetree/bindings/pwm/imx-pwm.txt | 2 +-
> Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 +-
> Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> index 9b9b185..8522bfb 100644
> --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> @@ -4,7 +4,7 @@ Required properties:
> - compatible: should be "fsl,<soc>-pwm"
> - reg: physical base address and length of the controller's registers
> - #pwm-cells: should be 2. The first cell specifies the per-chip index
> - of the PWM to use and the second cell is the duty cycle in nanoseconds.
> + of the PWM to use and the second cell is the period in nanoseconds.
> - interrupts: The interrupt for the pwm controller
>
> Example:
> diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
> index b16f4a5..d7946be6 100644
> --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
> @@ -4,7 +4,7 @@ Required properties:
> - compatible: should be "fsl,imx23-pwm"
> - reg: physical base address and length of the controller's registers
> - #pwm-cells: should be 2. The first cell specifies the per-chip index
> - of the PWM to use and the second cell is the duty cycle in nanoseconds.
> + of the PWM to use and the second cell is the period in nanoseconds.
> - fsl,pwm-number: the number of PWM devices
>
> Example:
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index bbbeedb..01438ec 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -7,7 +7,7 @@ Required properties:
> - reg: physical base address and length of the controller's registers
> - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
> first cell specifies the per-chip index of the PWM to use and the second
> - cell is the duty cycle in nanoseconds.
> + cell is the period in nanoseconds.
>
> Example:
>
> --
> 1.7.12.2
>
>
--
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] pwm: dt: Fix description of second PWM cell
2012-10-01 6:47 [PATCH] pwm: dt: Fix description of second PWM cell Thierry Reding
2012-10-05 15:24 ` Sascha Hauer
@ 2012-10-07 3:16 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Shawn Guo @ 2012-10-07 3:16 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-kernel, Sascha Hauer, Philipp Zabel,
Benoît Thébaudeau, Stephen Warren
On Mon, Oct 01, 2012 at 08:47:33AM +0200, Thierry Reding wrote:
> The second cell in the PWM specifier denotes the period in nanoseconds,
> not the duty cycle. The latter can be freely configured at runtime and
> a PWM with a fixed duty cycle would be rather pointless.
>
> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> ---
> Documentation/devicetree/bindings/pwm/imx-pwm.txt | 2 +-
> Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 +-
Acked-by: Shawn Guo <shawn.guo@linaro.org>
> Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> index 9b9b185..8522bfb 100644
> --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
> @@ -4,7 +4,7 @@ Required properties:
> - compatible: should be "fsl,<soc>-pwm"
> - reg: physical base address and length of the controller's registers
> - #pwm-cells: should be 2. The first cell specifies the per-chip index
> - of the PWM to use and the second cell is the duty cycle in nanoseconds.
> + of the PWM to use and the second cell is the period in nanoseconds.
> - interrupts: The interrupt for the pwm controller
>
> Example:
> diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
> index b16f4a5..d7946be6 100644
> --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
> @@ -4,7 +4,7 @@ Required properties:
> - compatible: should be "fsl,imx23-pwm"
> - reg: physical base address and length of the controller's registers
> - #pwm-cells: should be 2. The first cell specifies the per-chip index
> - of the PWM to use and the second cell is the duty cycle in nanoseconds.
> + of the PWM to use and the second cell is the period in nanoseconds.
> - fsl,pwm-number: the number of PWM devices
>
> Example:
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index bbbeedb..01438ec 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -7,7 +7,7 @@ Required properties:
> - reg: physical base address and length of the controller's registers
> - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
> first cell specifies the per-chip index of the PWM to use and the second
> - cell is the duty cycle in nanoseconds.
> + cell is the period in nanoseconds.
>
> Example:
>
> --
> 1.7.12.2
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-10-07 3:16 UTC | newest]
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2012-10-01 6:47 [PATCH] pwm: dt: Fix description of second PWM cell Thierry Reding
2012-10-05 15:24 ` Sascha Hauer
2012-10-07 3:16 ` Shawn Guo
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