Re: [PATCH] Revert 9fc2105aeaaf56b0cf75296a84702d0f9e64437b to fix pyaudio (and probably more)

[Catalin Marinas <catalin.marinas@arm.com>]

On Wed, Jan 07, 2015 at 01:20:06AM +0000, Linus Torvalds wrote:
> On Tue, Jan 6, 2015 at 3:42 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> >>
> >> That's what bogomips *is*, for chrissake! It's a bogus measure of how
> >> many times you go through the delay loop.
> >
> > I think that's where the misunderstanding is. We don't have any idea
> > how many times we go through the delay loop. We just go through the
> > delay loop until the counter (driven by an independent frequency)
> > changes X times.
> 
> .. and that's exactly what we do on x86 too with the TSC. It's fine.

I may be mistaken but isn't TSC somehow related to the CPU frequency on
x86?

On ARM, the generic/architected timer is not. It's just a timer+counter
(used as clocksource and event generator in Linux) clocked at a
frequency completely independent from the CPU frequency, *no* relation
between the two.

I think a better comparison would be to HPET rather than TSC. But on x86
we use HPET to calibrate the TSC and use the TSC for the delay loop. If
on x86 the BogoMIPS was changed to report the HPET frequency, would you
be ok with it?

> > With the current arm timer-based (and arm64) implementation, the
> > reported BogoMIPS has nothing to do with the CPU benchmark. It just
> > tells you that a X MHz counter needs X*1000000/HZ ticks per jiffy.
> 
> Yes. And that's a valid bogomips. We've done that for ages on x86.

See above, my understanding of TSC is that the x86 BogoMIPS is at least
in some way closely related to the CPU frequency. That's more like a
perf counter on ARM counting the CPU cycles but we don't use it for
udelay() (as it may or may not be enabled in a production system).

-- 
Catalin