Re: [PATCH v3] x86: move cacheinfo sysfs to generic cacheinfo infrastructure

[Borislav Petkov <bp@suse.de>]

On Tue, Mar 10, 2015 at 02:22:22PM +0000, Sudeep Holla wrote:
> I was able to reproduce this and now I realise I had CONFIG_AMD_NB
> disabled in my config earlier which hid this issue previously, sorry
> for that.
> 
> The below patch fixed the issue on my Intel i7 box. I can post this
> separately if required.
> 
> Regards,
> Sudeep
> 
> From b081cbf26071f4c8ce51f270931387415ab1a06c Mon Sep 17 00:00:00 2001
> From: Sudeep Holla <sudeep.holla@arm.com>
> Date: Tue, 10 Mar 2015 13:49:58 +0000
> Subject: [PATCH] x86: cacheinfo: fix cache_get_priv_group for Intel
> processors
> 
> The private pointer provided by the cacheinfo is used to implement
> the AMD L3 cache specific attributes using the northbridge pointer
> obtained through cpuid4 registers. However, it's populated even on
> Intel processors for Level 3 cache. This results in failure of

Do we need it populated on Intel?

Because if not, we can leave it NULL there and do only

	if (this_leaf->level < 3 || !nb)
		return NULL;

No?

Thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--