From: Peter Zijlstra <peterz@infradead.org>
To: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org, Oleg Nesterov <oleg@redhat.com>,
Ingo Molnar <mingo@kernel.org>
Subject: Re: Q: schedule() and implied barriers on arm64
Date: Fri, 16 Oct 2015 18:39:15 +0200 [thread overview]
Message-ID: <20151016163915.GB3816@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20151016162824.GS3910@linux.vnet.ibm.com>
On Fri, Oct 16, 2015 at 09:28:24AM -0700, Paul E. McKenney wrote:
> > Maybe some previous RCU variant relied on this?
>
> Yes, older versions did rely on this. Now, only the CPU itself observes
> RCU's state changes during context switch. I couldn't tell you exactly
> when this changed. :-/
>
> With the exception of some synchronize_sched_expedited() cases, but in
> those cases, RCU code acquires the CPU's leaf rcu_node structure's
> ->lock, and with the required strong transitivity.
OK, so I can scrap this 'requirement' from my list. All sorted, thanks!
> > > Well, arm64 might well need smp_mb__after_unlock_lock() to be non-empty.
> >
> > Its UNLOCK+LOCK should be RCsc, so that should be good. Its just that
> > LOCK+UNLOCK isn't anything.
>
> Ah! If RCU relies on LOCK+UNLOCK being a barrier of any sort, that is a
> bug in RCU that needs fixing.
Don't think RCU does that, But its what schedule() provides in the
weakest case. Hence my question here.
next prev parent reply other threads:[~2015-10-16 16:39 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 15:18 Peter Zijlstra
2015-10-16 16:04 ` Paul E. McKenney
2015-10-16 16:16 ` Peter Zijlstra
2015-10-16 16:28 ` Paul E. McKenney
2015-10-16 16:39 ` Peter Zijlstra [this message]
2015-10-16 16:55 ` Catalin Marinas
2015-10-16 17:28 ` Paul E. McKenney
2015-10-16 19:07 ` Peter Zijlstra
2015-10-16 19:20 ` Paul E. McKenney
2015-10-19 15:18 ` Catalin Marinas
2015-10-16 19:06 ` Peter Zijlstra
2015-10-19 7:06 ` Ingo Molnar
2015-10-19 9:04 ` Peter Zijlstra
2015-10-19 15:21 ` Catalin Marinas
2015-10-19 16:24 ` Peter Zijlstra
2015-10-20 8:37 ` Ingo Molnar
2015-10-27 16:19 ` Will Deacon
2015-10-27 18:40 ` Peter Zijlstra
2015-10-28 10:39 ` Will Deacon
2015-10-16 17:11 ` Catalin Marinas
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