From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Oleg Nesterov <oleg@redhat.com>, Ingo Molnar <mingo@kernel.org>
Subject: Re: Q: schedule() and implied barriers on arm64
Date: Fri, 16 Oct 2015 12:20:51 -0700 [thread overview]
Message-ID: <20151016192051.GX3910@linux.vnet.ibm.com> (raw)
In-Reply-To: <20151016190741.GD3816@twins.programming.kicks-ass.net>
On Fri, Oct 16, 2015 at 09:07:41PM +0200, Peter Zijlstra wrote:
> On Fri, Oct 16, 2015 at 10:28:11AM -0700, Paul E. McKenney wrote:
> > In other words, if task2() acquires the lock after task1() releases it,
> > all CPUs must agree on the order of the operations in the two critical
> > sections, even if these other CPUs don't acquire the lock.
> >
> > This same guarantee is needed if task1() and then task2() run in
> > succession on the same CPU with no additional synchronization of any sort.
> >
> > Does this work on arm64?
>
> Yes, their load-acquire and store-release are RCsc.
Whew!!!
Thanx, Paul
next prev parent reply other threads:[~2015-10-16 19:20 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 15:18 Peter Zijlstra
2015-10-16 16:04 ` Paul E. McKenney
2015-10-16 16:16 ` Peter Zijlstra
2015-10-16 16:28 ` Paul E. McKenney
2015-10-16 16:39 ` Peter Zijlstra
2015-10-16 16:55 ` Catalin Marinas
2015-10-16 17:28 ` Paul E. McKenney
2015-10-16 19:07 ` Peter Zijlstra
2015-10-16 19:20 ` Paul E. McKenney [this message]
2015-10-19 15:18 ` Catalin Marinas
2015-10-16 19:06 ` Peter Zijlstra
2015-10-19 7:06 ` Ingo Molnar
2015-10-19 9:04 ` Peter Zijlstra
2015-10-19 15:21 ` Catalin Marinas
2015-10-19 16:24 ` Peter Zijlstra
2015-10-20 8:37 ` Ingo Molnar
2015-10-27 16:19 ` Will Deacon
2015-10-27 18:40 ` Peter Zijlstra
2015-10-28 10:39 ` Will Deacon
2015-10-16 17:11 ` Catalin Marinas
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