From: Borislav Petkov <bp@alien8.de>
To: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Cc: lukasz.anaczkowski@intel.com, mchehab@osg.samsung.com,
dougthompson@xmission.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] sb_edac: Setting fixed DIMM width for Xeon Knights Landing platform.
Date: Fri, 11 Dec 2015 16:59:13 +0100 [thread overview]
Message-ID: <20151211155913.GB4815@pd.tnic> (raw)
In-Reply-To: <1449840082-18673-1-git-send-email-hubert.chrzaniuk@intel.com>
On Fri, Dec 11, 2015 at 02:21:22PM +0100, Hubert Chrzaniuk wrote:
> Knights Landing does not come with register that could be used
> to fetch DIMM width. However the value is fixed for this architecture
> so it can be hardcoded.
>
> Fixes: d0cdf900314 (sb_edac: Add Knights Landing (Xeon Phi gen 2) support)
> Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
> ---
> drivers/edac/sb_edac.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Applied, thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
next prev parent reply other threads:[~2015-12-11 15:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-11 13:21 Hubert Chrzaniuk
2015-12-11 15:59 ` Borislav Petkov [this message]
-- strict thread matches above, loose matches on Subject: below --
2015-12-11 13:16 Hubert Chrzaniuk
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