* [PATCH] ARM: tegra: remove redundant ARM_L1_CACHE_SHIFT_6 select
@ 2016-01-23 8:55 Masahiro Yamada
2016-01-25 12:24 ` Thierry Reding
0 siblings, 1 reply; 2+ messages in thread
From: Masahiro Yamada @ 2016-01-23 8:55 UTC (permalink / raw)
To: linux-arm-kernel, linux-tegra
Cc: Alexandre Courbot, Thierry Reding, Arnd Bergmann, Stephen Warren,
Masahiro Yamada, Mikko Perttunen, linux-kernel, Tuomas Tynkkynen
These two are both ARMv7 SoCs. They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.
Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/soc/tegra/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index d0c3c3e..03089ad 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -31,7 +31,6 @@ config ARCH_TEGRA_3x_SOC
config ARCH_TEGRA_114_SOC
bool "Enable support for Tegra114 family"
select ARM_ERRATA_798181 if SMP
- select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA114
select TEGRA_TIMER
@@ -41,7 +40,6 @@ config ARCH_TEGRA_114_SOC
config ARCH_TEGRA_124_SOC
bool "Enable support for Tegra124 family"
- select ARM_L1_CACHE_SHIFT_6
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA124
select TEGRA_TIMER
--
1.9.1
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH] ARM: tegra: remove redundant ARM_L1_CACHE_SHIFT_6 select
2016-01-23 8:55 [PATCH] ARM: tegra: remove redundant ARM_L1_CACHE_SHIFT_6 select Masahiro Yamada
@ 2016-01-25 12:24 ` Thierry Reding
0 siblings, 0 replies; 2+ messages in thread
From: Thierry Reding @ 2016-01-25 12:24 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-arm-kernel, linux-tegra, Alexandre Courbot, Arnd Bergmann,
Stephen Warren, Mikko Perttunen, linux-kernel, Tuomas Tynkkynen
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On Sat, Jan 23, 2016 at 05:55:30PM +0900, Masahiro Yamada wrote:
> These two are both ARMv7 SoCs. They need not explicitly select
> ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.
>
> Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
> cachelines for ARMv7 CPUs").
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> drivers/soc/tegra/Kconfig | 2 --
> 1 file changed, 2 deletions(-)
Applied, thanks.
Thierry
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2016-01-23 8:55 [PATCH] ARM: tegra: remove redundant ARM_L1_CACHE_SHIFT_6 select Masahiro Yamada
2016-01-25 12:24 ` Thierry Reding
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