[PATCH 1/4] x86/kernel: Remove requirement that TSC ADJUST must be 0 on socket 0

[<mike.travis@hpe.com>]

[-- Attachment #1: add-base-nonzero --]
[-- Type: text/plain, Size: 2320 bytes --]

Remove the requirement that the TSC ADJUST value for socket 0 must
be zero.  This is the case when there are multiple chassis are being
reset asynchronously with each other and socket 0 may not necessarily
be starting first.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: Russ Anderson <russ.anderson@hpe.com>
---
 arch/x86/kernel/tsc_sync.c |   29 +++--------------------------
 1 file changed, 3 insertions(+), 26 deletions(-)

--- linux.orig/arch/x86/kernel/tsc_sync.c
+++ linux/arch/x86/kernel/tsc_sync.c
@@ -58,29 +58,6 @@ void tsc_verify_tsc_adjust(bool resume)
 	}
 }
 
-static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
-				   unsigned int cpu, bool bootcpu)
-{
-	/*
-	 * First online CPU in a package stores the boot value in the
-	 * adjustment value. This value might change later via the sync
-	 * mechanism. If that fails we still can yell about boot values not
-	 * being consistent.
-	 *
-	 * On the boot cpu we just force set the ADJUST value to 0 if it's
-	 * non zero. We don't do that on non boot cpus because physical
-	 * hotplug should have set the ADJUST register to a value > 0 so
-	 * the TSC is in sync with the already running cpus.
-	 */
-	if (bootcpu && bootval != 0) {
-		pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", cpu,
-			bootval);
-		wrmsrl(MSR_IA32_TSC_ADJUST, 0);
-		bootval = 0;
-	}
-	cur->adjusted = bootval;
-}
-
 #ifndef CONFIG_SMP
 bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
 {
@@ -92,8 +69,8 @@ bool __init tsc_store_and_check_tsc_adju
 
 	rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
 	cur->bootval = bootval;
+	cur->adjusted = bootval;
 	cur->nextcheck = jiffies + HZ;
-	tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
 	return false;
 }
 
@@ -114,6 +91,7 @@ bool tsc_store_and_check_tsc_adjust(bool
 
 	rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
 	cur->bootval = bootval;
+	cur->adjusted = bootval;
 	cur->nextcheck = jiffies + HZ;
 	cur->warned = false;
 
@@ -128,8 +106,7 @@ bool tsc_store_and_check_tsc_adjust(bool
 	refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
 
 	if (refcpu >= nr_cpu_ids) {
-		tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
-				       bootcpu);
+		cur->adjusted = bootval;
 		return false;
 	}
 

--