* [PATCH] x86: clean up confusing x86_mask
@ 2017-12-29 14:32 Jia Zhang
2017-12-31 11:43 ` kbuild test robot
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jia Zhang @ 2017-12-29 14:32 UTC (permalink / raw)
To: bp, mingo; +Cc: hpa, tglx, tony.luck, x86, linux-kernel, Jia Zhang
x86_mask is a confusing name. It is hard to associate it with
processor's stepping.
Additionally, correct an indent issue in lib/cpu.c.
Signed-off-by: Jia Zhang <qianyue.zj@alibaba-inc.com>
---
arch/x86/events/intel/core.c | 2 +-
arch/x86/events/intel/lbr.c | 2 +-
arch/x86/events/intel/p6.c | 2 +-
arch/x86/include/asm/acpi.h | 2 +-
arch/x86/include/asm/processor.h | 2 +-
arch/x86/kernel/amd_nb.c | 2 +-
arch/x86/kernel/apic/apic.c | 6 +++---
arch/x86/kernel/asm-offsets_32.c | 2 +-
arch/x86/kernel/cpu/amd.c | 28 ++++++++++++++--------------
arch/x86/kernel/cpu/centaur.c | 4 ++--
arch/x86/kernel/cpu/common.c | 8 ++++----
arch/x86/kernel/cpu/cyrix.c | 2 +-
arch/x86/kernel/cpu/intel.c | 16 ++++++++--------
arch/x86/kernel/cpu/intel_rdt.c | 2 +-
arch/x86/kernel/cpu/microcode/intel.c | 2 +-
arch/x86/kernel/cpu/mtrr/generic.c | 2 +-
arch/x86/kernel/cpu/mtrr/main.c | 4 ++--
arch/x86/kernel/cpu/proc.c | 4 ++--
arch/x86/kernel/head_32.S | 4 ++--
arch/x86/kernel/mpparse.c | 2 +-
arch/x86/lib/cpu.c | 2 +-
21 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 09c26a4..1c25584 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3559,7 +3559,7 @@ static int intel_snb_pebs_broken(int cpu)
break;
case INTEL_FAM6_SANDYBRIDGE_X:
- switch (cpu_data(cpu).x86_mask) {
+ switch (cpu_data(cpu).x86_stepping) {
case 6: rev = 0x618; break;
case 7: rev = 0x70c; break;
}
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index ae64d0b..cf372b9 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1186,7 +1186,7 @@ void __init intel_pmu_lbr_init_atom(void)
* on PMU interrupt
*/
if (boot_cpu_data.x86_model == 28
- && boot_cpu_data.x86_mask < 10) {
+ && boot_cpu_data.x86_stepping < 10) {
pr_cont("LBR disabled due to erratum");
return;
}
diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
index a5604c3..408879b 100644
--- a/arch/x86/events/intel/p6.c
+++ b/arch/x86/events/intel/p6.c
@@ -234,7 +234,7 @@ static void p6_pmu_enable_event(struct perf_event *event)
static __init void p6_pmu_rdpmc_quirk(void)
{
- if (boot_cpu_data.x86_mask < 9) {
+ if (boot_cpu_data.x86_stepping < 9) {
/*
* PPro erratum 26; fixed in stepping 9 and above.
*/
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 8d0ec9d..f077401 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -94,7 +94,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
if (boot_cpu_data.x86 == 0x0F &&
boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
boot_cpu_data.x86_model <= 0x05 &&
- boot_cpu_data.x86_mask < 0x0A)
+ boot_cpu_data.x86_stepping < 0x0A)
return 1;
else if (boot_cpu_has(X86_BUG_AMD_APIC_C1E))
return 1;
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index cad8dab..b47944f 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -91,7 +91,7 @@ struct cpuinfo_x86 {
__u8 x86; /* CPU family */
__u8 x86_vendor; /* CPU vendor */
__u8 x86_model;
- __u8 x86_mask;
+ __u8 x86_stepping;
#ifdef CONFIG_X86_64
/* Number of 4K pages in DTLB/ITLB combined(in pages): */
int x86_tlbsize;
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 6db28f1..c88e0b1 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -235,7 +235,7 @@ int amd_cache_northbridges(void)
if (boot_cpu_data.x86 == 0x10 &&
boot_cpu_data.x86_model >= 0x8 &&
(boot_cpu_data.x86_model > 0x9 ||
- boot_cpu_data.x86_mask >= 0x1))
+ boot_cpu_data.x86_stepping >= 0x1))
amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
if (boot_cpu_data.x86 == 0x15)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 6e272f3..742aed4 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -546,7 +546,7 @@ static void lapic_timer_broadcast(const struct cpumask *mask)
static u32 hsx_deadline_rev(void)
{
- switch (boot_cpu_data.x86_mask) {
+ switch (boot_cpu_data.x86_stepping) {
case 0x02: return 0x3a; /* EP */
case 0x04: return 0x0f; /* EX */
}
@@ -556,7 +556,7 @@ static u32 hsx_deadline_rev(void)
static u32 bdx_deadline_rev(void)
{
- switch (boot_cpu_data.x86_mask) {
+ switch (boot_cpu_data.x86_stepping) {
case 0x02: return 0x00000011;
case 0x03: return 0x0700000e;
case 0x04: return 0x0f00000c;
@@ -568,7 +568,7 @@ static u32 bdx_deadline_rev(void)
static u32 skx_deadline_rev(void)
{
- switch (boot_cpu_data.x86_mask) {
+ switch (boot_cpu_data.x86_stepping) {
case 0x03: return 0x01000136;
case 0x04: return 0x02000014;
}
diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
index fa1261e..f91ba53 100644
--- a/arch/x86/kernel/asm-offsets_32.c
+++ b/arch/x86/kernel/asm-offsets_32.c
@@ -18,7 +18,7 @@ void foo(void)
OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
- OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
+ OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcb75dc..f4ebe7e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -119,7 +119,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
return;
}
- if (c->x86_model == 6 && c->x86_mask == 1) {
+ if (c->x86_model == 6 && c->x86_stepping == 1) {
const int K6_BUG_LOOP = 1000000;
int n;
void (*f_vide)(void);
@@ -149,7 +149,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
/* K6 with old style WHCR */
if (c->x86_model < 8 ||
- (c->x86_model == 8 && c->x86_mask < 8)) {
+ (c->x86_model == 8 && c->x86_stepping < 8)) {
/* We can only write allocate on the low 508Mb */
if (mbytes > 508)
mbytes = 508;
@@ -168,7 +168,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
return;
}
- if ((c->x86_model == 8 && c->x86_mask > 7) ||
+ if ((c->x86_model == 8 && c->x86_stepping > 7) ||
c->x86_model == 9 || c->x86_model == 13) {
/* The more serious chips .. */
@@ -221,7 +221,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
* As per AMD technical note 27212 0.2
*/
- if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
+ if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
rdmsr(MSR_K7_CLK_CTL, l, h);
if ((l & 0xfff00000) != 0x20000000) {
pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
@@ -241,12 +241,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* but they are not certified as MP capable.
*/
/* Athlon 660/661 is valid. */
- if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
- (c->x86_mask == 1)))
+ if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
+ (c->x86_stepping == 1)))
return;
/* Duron 670 is valid */
- if ((c->x86_model == 7) && (c->x86_mask == 0))
+ if ((c->x86_model == 7) && (c->x86_stepping == 0))
return;
/*
@@ -256,8 +256,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
* more.
*/
- if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
- ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
+ if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
+ ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
(c->x86_model > 7))
if (cpu_has(c, X86_FEATURE_MP))
return;
@@ -583,7 +583,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
/* Set MTRR capability flag if appropriate */
if (c->x86 == 5)
if (c->x86_model == 13 || c->x86_model == 9 ||
- (c->x86_model == 8 && c->x86_mask >= 8))
+ (c->x86_model == 8 && c->x86_stepping >= 8))
set_cpu_cap(c, X86_FEATURE_K6_MTRR);
#endif
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
@@ -769,7 +769,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
* all up to and including B1.
*/
- if (c->x86_model <= 1 && c->x86_mask <= 1)
+ if (c->x86_model <= 1 && c->x86_stepping <= 1)
set_cpu_cap(c, X86_FEATURE_CPB);
}
@@ -856,11 +856,11 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
/* AMD errata T13 (order #21922) */
if ((c->x86 == 6)) {
/* Duron Rev A0 */
- if (c->x86_model == 3 && c->x86_mask == 0)
+ if (c->x86_model == 3 && c->x86_stepping == 0)
size = 64;
/* Tbird rev A1/A2 */
if (c->x86_model == 4 &&
- (c->x86_mask == 0 || c->x86_mask == 1))
+ (c->x86_stepping == 0 || c->x86_stepping == 1))
size = 256;
}
return size;
@@ -997,7 +997,7 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
}
/* OSVW unavailable or ID unknown, match family-model-stepping range */
- ms = (cpu->x86_model << 4) | cpu->x86_mask;
+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
while ((range = *erratum++))
if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
(ms >= AMD_MODEL_RANGE_START(range)) &&
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 68bc6d9..595be77 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -136,7 +136,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, X86_FEATURE_TSC);
break;
case 8:
- switch (c->x86_mask) {
+ switch (c->x86_stepping) {
default:
name = "2";
break;
@@ -211,7 +211,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
* - Note, it seems this may only be in engineering samples.
*/
if ((c->x86 == 6) && (c->x86_model == 9) &&
- (c->x86_mask == 1) && (size == 65))
+ (c->x86_stepping == 1) && (size == 65))
size -= 1;
return size;
}
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c9757f0..367cb27 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -729,7 +729,7 @@ void cpu_detect(struct cpuinfo_x86 *c)
cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
c->x86 = x86_family(tfms);
c->x86_model = x86_model(tfms);
- c->x86_mask = x86_stepping(tfms);
+ c->x86_stepping = x86_stepping(tfms);
if (cap0 & (1<<19)) {
c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
@@ -1119,7 +1119,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
c->loops_per_jiffy = loops_per_jiffy;
c->x86_cache_size = -1;
c->x86_vendor = X86_VENDOR_UNKNOWN;
- c->x86_model = c->x86_mask = 0; /* So far unknown... */
+ c->x86_model = c->x86_stepping = 0; /* So far unknown... */
c->x86_vendor_id[0] = '\0'; /* Unset */
c->x86_model_id[0] = '\0'; /* Unset */
c->x86_max_cores = 1;
@@ -1311,8 +1311,8 @@ void print_cpu_info(struct cpuinfo_x86 *c)
pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
- if (c->x86_mask || c->cpuid_level >= 0)
- pr_cont(", stepping: 0x%x)\n", c->x86_mask);
+ if (c->x86_stepping || c->cpuid_level >= 0)
+ pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
else
pr_cont(")\n");
}
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 6b4bb33..8949b7a 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -215,7 +215,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
/* common case step number/rev -- exceptions handled below */
c->x86_model = (dir1 >> 4) + 1;
- c->x86_mask = dir1 & 0xf;
+ c->x86_stepping = dir1 & 0xf;
/* Now cook; the original recipe is by Channing Corn, from Cyrix.
* We do the same thing for each generation: we work out
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b1af220..ae783a9 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -130,7 +130,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
* need the microcode to have already been loaded... so if it is
* not, recommend a BIOS update and disable large pages.
*/
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
c->microcode < 0x20e) {
pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
clear_cpu_cap(c, X86_FEATURE_PSE);
@@ -146,7 +146,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
/* CPUID workaround for 0F33/0F34 CPU */
if (c->x86 == 0xF && c->x86_model == 0x3
- && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
+ && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
c->x86_phys_bits = 36;
/*
@@ -244,7 +244,7 @@ int ppro_with_ram_bug(void)
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
boot_cpu_data.x86 == 6 &&
boot_cpu_data.x86_model == 1 &&
- boot_cpu_data.x86_mask < 8) {
+ boot_cpu_data.x86_stepping < 8) {
pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
return 1;
}
@@ -261,7 +261,7 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
* Mask B, Pentium, but not Pentium MMX
*/
if (c->x86 == 5 &&
- c->x86_mask >= 1 && c->x86_mask <= 4 &&
+ c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
c->x86_model <= 3) {
/*
* Remember we have B step Pentia with bugs
@@ -304,7 +304,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
* model 3 mask 3
*/
- if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
+ if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
clear_cpu_cap(c, X86_FEATURE_SEP);
/*
@@ -322,7 +322,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
* P4 Xeon erratum 037 workaround.
* Hardware prefetcher may cause stale data to be loaded into the cache.
*/
- if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
+ if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
if (msr_set_bit(MSR_IA32_MISC_ENABLE,
MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
pr_info("CPU: C0 stepping P4 Xeon detected.\n");
@@ -337,7 +337,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
* Specification Update").
*/
if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
- (c->x86_mask < 0x6 || c->x86_mask == 0xb))
+ (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
set_cpu_bug(c, X86_BUG_11AP);
@@ -584,7 +584,7 @@ static void init_intel(struct cpuinfo_x86 *c)
case 6:
if (l2 == 128)
p = "Celeron (Mendocino)";
- else if (c->x86_mask == 0 || c->x86_mask == 5)
+ else if (c->x86_stepping == 0 || c->x86_stepping == 5)
p = "Celeron-A";
break;
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 88dcf84..bfe552b 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -771,7 +771,7 @@ static __init void rdt_quirks(void)
cache_alloc_hsw_probe();
break;
case INTEL_FAM6_SKYLAKE_X:
- if (boot_cpu_data.x86_mask <= 4)
+ if (boot_cpu_data.x86_stepping <= 4)
set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
}
}
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 8ccdca6..99af05f 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -930,7 +930,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
return UCODE_NFOUND;
sprintf(name, "intel-ucode/%02x-%02x-%02x",
- c->x86, c->x86_model, c->x86_mask);
+ c->x86, c->x86_model, c->x86_stepping);
if (request_firmware_direct(&firmware, name, device)) {
pr_debug("data file %s load failed\n", name);
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index fdc5521..e12ee86 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -859,7 +859,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
*/
if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
boot_cpu_data.x86_model == 1 &&
- boot_cpu_data.x86_mask <= 7) {
+ boot_cpu_data.x86_stepping <= 7) {
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
return -EINVAL;
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 40d5a8a..7468de4 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -711,8 +711,8 @@ void __init mtrr_bp_init(void)
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
boot_cpu_data.x86 == 0xF &&
boot_cpu_data.x86_model == 0x3 &&
- (boot_cpu_data.x86_mask == 0x3 ||
- boot_cpu_data.x86_mask == 0x4))
+ (boot_cpu_data.x86_stepping == 0x3 ||
+ boot_cpu_data.x86_stepping == 0x4))
phys_addr = 36;
size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index e7eceda..ee4cc38 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -72,8 +72,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
c->x86_model,
c->x86_model_id[0] ? c->x86_model_id : "unknown");
- if (c->x86_mask || c->cpuid_level >= 0)
- seq_printf(m, "stepping\t: %d\n", c->x86_mask);
+ if (c->x86_stepping || c->cpuid_level >= 0)
+ seq_printf(m, "stepping\t: %d\n", c->x86_stepping);
else
seq_puts(m, "stepping\t: unknown\n");
if (c->microcode)
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index c290209..b59e4fb 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -37,7 +37,7 @@
#define X86 new_cpu_data+CPUINFO_x86
#define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
#define X86_MODEL new_cpu_data+CPUINFO_x86_model
-#define X86_MASK new_cpu_data+CPUINFO_x86_mask
+#define X86_STEPPING new_cpu_data+CPUINFO_x86_stepping
#define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
#define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
@@ -332,7 +332,7 @@ ENTRY(startup_32_smp)
shrb $4,%al
movb %al,X86_MODEL
andb $0x0f,%cl # mask mask revision
- movb %cl,X86_MASK
+ movb %cl,X86_STEPPING
movl %edx,X86_CAPABILITY
.Lis486:
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 3a4b128..bc6bc66 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -407,7 +407,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
processor.cpuflag = CPU_ENABLED;
processor.cpufeature = (boot_cpu_data.x86 << 8) |
- (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
+ (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
processor.reserved[0] = 0;
processor.reserved[1] = 0;
diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c
index d6f848d..2dd1fe13 100644
--- a/arch/x86/lib/cpu.c
+++ b/arch/x86/lib/cpu.c
@@ -18,7 +18,7 @@ unsigned int x86_model(unsigned int sig)
{
unsigned int fam, model;
- fam = x86_family(sig);
+ fam = x86_family(sig);
model = (sig >> 4) & 0xf;
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86: clean up confusing x86_mask
2017-12-29 14:32 [PATCH] x86: clean up confusing x86_mask Jia Zhang
@ 2017-12-31 11:43 ` kbuild test robot
2017-12-31 11:44 ` kbuild test robot
2017-12-31 16:55 ` kbuild test robot
2 siblings, 0 replies; 4+ messages in thread
From: kbuild test robot @ 2017-12-31 11:43 UTC (permalink / raw)
To: Jia Zhang
Cc: kbuild-all, bp, mingo, hpa, tglx, tony.luck, x86, linux-kernel,
Jia Zhang
[-- Attachment #1: Type: text/plain, Size: 19137 bytes --]
Hi Jia,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.15-rc5]
[also build test ERROR on next-20171222]
[cannot apply to tip/x86/core]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jia-Zhang/x86-clean-up-confusing-x86_mask/20171231-182946
config: x86_64-acpi-redef (attached as .config)
compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:14:0,
from drivers//cpufreq/speedstep-lib.c:13:
drivers//cpufreq/speedstep-lib.c: In function 'speedstep_detect_processor':
>> drivers//cpufreq/speedstep-lib.c:275:57: error: 'struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
^
include/linux/printk.h:136:17: note: in definition of macro 'no_printk'
printk(fmt, ##__VA_ARGS__); \
^~~~~~~~~~~
>> drivers//cpufreq/speedstep-lib.c:275:3: note: in expansion of macro 'pr_debug'
pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
^~~~~~~~
drivers//cpufreq/speedstep-lib.c:277:14: error: 'struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
switch (c->x86_mask) {
^~~~~~~~
x86_model
drivers//cpufreq/speedstep-lib.c:364:11: error: 'struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
if (c->x86_mask == 0x01) {
^~~~~~~~
x86_model
--
drivers//cpufreq/speedstep-centrino.c: In function 'centrino_verify_cpu_id':
>> drivers//cpufreq/speedstep-centrino.c:280:10: error: 'const struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
(c->x86_mask == x->x86_mask))
^~~~~~~~
x86_model
--
drivers//cpufreq/p4-clockmod.c: In function 'cpufreq_p4_cpu_init':
>> drivers//cpufreq/p4-clockmod.c:171:51: error: 'struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
^~~~~~~~
x86_model
--
drivers//hwmon/hwmon-vid.c: In function 'vid_which_vrm':
>> drivers//hwmon/hwmon-vid.c:296:46: error: 'struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
^~~~~~~~
x86_model
--
drivers//hwmon/k10temp.c: In function 'has_erratum_319':
>> drivers//hwmon/k10temp.c:229:56: error: 'struct cpuinfo_x86' has no member named 'x86_mask'; did you mean 'x86_model'?
(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
^~~~~~~~
x86_model
>> drivers//hwmon/k10temp.c:230:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
vim +275 drivers//cpufreq/speedstep-lib.c
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 248
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 249
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 250 /*********************************************************************
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 251 * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 252 *********************************************************************/
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 253
fa8031ae drivers/cpufreq/speedstep-lib.c Andi Kleen 2012-01-26 254 /* Keep in sync with the x86_cpu_id tables in the different modules */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 255 unsigned int speedstep_detect_processor(void)
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 256 {
92cb7612 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Mike Travis 2007-10-19 257 struct cpuinfo_x86 *c = &cpu_data(0);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 258 u32 ebx, msr_lo, msr_hi;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 259
2d06d8c4 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dominik Brodowski 2011-03-27 260 pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 261
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 262 if ((c->x86_vendor != X86_VENDOR_INTEL) ||
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 263 ((c->x86 != 6) && (c->x86 != 0xF)))
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 264 return 0;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 265
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 266 if (c->x86 == 0xF) {
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 267 /* Intel Mobile Pentium 4-M
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 268 * or Intel Mobile Pentium 4 with 533 MHz FSB */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 269 if (c->x86_model != 2)
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 270 return 0;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 271
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 272 ebx = cpuid_ebx(0x00000001);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 273 ebx &= 0x000000FF;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 274
2d06d8c4 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dominik Brodowski 2011-03-27 @275 pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 276
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 277 switch (c->x86_mask) {
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 278 case 4:
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 279 /*
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 280 * B-stepping [M-P4-M]
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 281 * sample has ebx = 0x0f, production has 0x0e.
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 282 */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 283 if ((ebx == 0x0e) || (ebx == 0x0f))
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 284 return SPEEDSTEP_CPU_P4M;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 285 break;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 286 case 7:
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 287 /*
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 288 * C-stepping [M-P4-M]
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 289 * needs to have ebx=0x0e, else it's a celeron:
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 290 * cf. 25130917.pdf / page 7, footnote 5 even
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 291 * though 25072120.pdf / page 7 doesn't say
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 292 * samples are only of B-stepping...
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 293 */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 294 if (ebx == 0x0e)
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 295 return SPEEDSTEP_CPU_P4M;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 296 break;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 297 case 9:
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 298 /*
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 299 * D-stepping [M-P4-M or M-P4/533]
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 300 *
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 301 * this is totally strange: CPUID 0x0F29 is
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 302 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 303 * The latter need to be sorted out as they don't
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 304 * support speedstep.
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 305 * Celerons with CPUID 0x0F29 may have either
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 306 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 307 * specific.
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 308 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 309 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 310 * also, M-P4M HTs have ebx=0x8, too
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 311 * For now, they are distinguished by the model_id
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 312 * string
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 313 */
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 314 if ((ebx == 0x0e) ||
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 315 (strstr(c->x86_model_id,
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 316 "Mobile Intel(R) Pentium(R) 4") != NULL))
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 317 return SPEEDSTEP_CPU_P4M;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 318 break;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 319 default:
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 320 break;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 321 }
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 322 return 0;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 323 }
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 324
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 325 switch (c->x86_model) {
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 326 case 0x0B: /* Intel PIII [Tualatin] */
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 327 /* cpuid_ebx(1) is 0x04 for desktop PIII,
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 328 * 0x06 for mobile PIII-M */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 329 ebx = cpuid_ebx(0x00000001);
2d06d8c4 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dominik Brodowski 2011-03-27 330 pr_debug("ebx is %x\n", ebx);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 331
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 332 ebx &= 0x000000FF;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 333
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 334 if (ebx != 0x06)
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 335 return 0;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 336
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 337 /* So far all PIII-M processors support SpeedStep. See
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 338 * Intel's 24540640.pdf of June 2003
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 339 */
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 340 return SPEEDSTEP_CPU_PIII_T;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 341
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 342 case 0x08: /* Intel PIII [Coppermine] */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 343
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 344 /* all mobile PIII Coppermines have FSB 100 MHz
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 345 * ==> sort out a few desktop PIIIs. */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 346 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
2d06d8c4 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dominik Brodowski 2011-03-27 347 pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 348 msr_lo, msr_hi);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 349 msr_lo &= 0x00c0000;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 350 if (msr_lo != 0x0080000)
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 351 return 0;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 352
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 353 /*
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 354 * If the processor is a mobile version,
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 355 * platform ID has bit 50 set
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 356 * it has SpeedStep technology if either
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 357 * bit 56 or 57 is set
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 358 */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 359 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
2d06d8c4 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dominik Brodowski 2011-03-27 360 pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 361 msr_lo, msr_hi);
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 362 if ((msr_hi & (1<<18)) &&
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 363 (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 364 if (c->x86_mask == 0x01) {
2d06d8c4 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dominik Brodowski 2011-03-27 365 pr_debug("early PIII version\n");
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 366 return SPEEDSTEP_CPU_PIII_C_EARLY;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 367 } else
bbfebd66 arch/x86/kernel/cpu/cpufreq/speedstep-lib.c Dave Jones 2009-01-17 368 return SPEEDSTEP_CPU_PIII_C;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 369 }
9bc70e69 drivers/cpufreq/speedstep-lib.c Gustavo A. R. Silva 2017-10-12 370 /* fall through */
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 371 default:
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 372 return 0;
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 373 }
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 374 }
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 375 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 376
^1da177e arch/i386/kernel/cpu/cpufreq/speedstep-lib.c Linus Torvalds 2005-04-16 377
:::::: The code at line 275 was first introduced by commit
:::::: 2d06d8c49afdcc9bb35a85039fa50f0fe35bd40e [CPUFREQ] use dynamic debug instead of custom infrastructure
:::::: TO: Dominik Brodowski <linux@dominikbrodowski.net>
:::::: CC: Dave Jones <davej@redhat.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86: clean up confusing x86_mask
2017-12-29 14:32 [PATCH] x86: clean up confusing x86_mask Jia Zhang
2017-12-31 11:43 ` kbuild test robot
@ 2017-12-31 11:44 ` kbuild test robot
2017-12-31 16:55 ` kbuild test robot
2 siblings, 0 replies; 4+ messages in thread
From: kbuild test robot @ 2017-12-31 11:44 UTC (permalink / raw)
To: Jia Zhang
Cc: kbuild-all, bp, mingo, hpa, tglx, tony.luck, x86, linux-kernel,
Jia Zhang
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Hi Jia,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.15-rc5]
[also build test ERROR on next-20171222]
[cannot apply to tip/x86/core]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jia-Zhang/x86-clean-up-confusing-x86_mask/20171231-182946
config: i386-randconfig-a0-201753 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers//hwmon/hwmon-vid.c: In function 'vid_which_vrm':
>> drivers//hwmon/hwmon-vid.c:296:44: error: 'struct cpuinfo_x86' has no member named 'x86_mask'
vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
^
vim +296 drivers//hwmon/hwmon-vid.c
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 287
734a12a3 drivers/hwmon/hwmon-vid.c Rudolf Marek 2005-12-18 288 u8 vid_which_vrm(void)
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 289 {
92cb7612 drivers/hwmon/hwmon-vid.c Mike Travis 2007-10-19 290 struct cpuinfo_x86 *c = &cpu_data(0);
3230f704 drivers/hwmon/hwmon-vid.c Guenter Roeck 2012-01-24 291 u8 vrm_ret;
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 292
da97a5a3 drivers/hwmon/hwmon-vid.c Jean Delvare 2005-07-31 293 if (c->x86 < 6) /* Any CPU with family lower than 6 */
3230f704 drivers/hwmon/hwmon-vid.c Guenter Roeck 2012-01-24 294 return 0; /* doesn't have VID */
3230f704 drivers/hwmon/hwmon-vid.c Guenter Roeck 2012-01-24 295
3230f704 drivers/hwmon/hwmon-vid.c Guenter Roeck 2012-01-24 @296 vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
0a88f4b5 drivers/hwmon/hwmon-vid.c Jean Delvare 2011-07-25 297 if (vrm_ret == 134)
0a88f4b5 drivers/hwmon/hwmon-vid.c Jean Delvare 2011-07-25 298 vrm_ret = get_via_model_d_vrm();
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 299 if (vrm_ret == 0)
1f923c7a drivers/hwmon/hwmon-vid.c Joe Perches 2010-10-20 300 pr_info("Unknown VRM version of your x86 CPU\n");
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 301 return vrm_ret;
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 302 }
^1da177e drivers/i2c/i2c-sensor-vid.c Linus Torvalds 2005-04-16 303
:::::: The code at line 296 was first introduced by commit
:::::: 3230f7049e6325c27d6d40f2a1547cf75bc4ddff hwmon: (hwmon-vid) Add new entries to VRM model table
:::::: TO: Guenter Roeck <linux@roeck-us.net>
:::::: CC: Guenter Roeck <guenter.roeck@ericsson.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] x86: clean up confusing x86_mask
2017-12-29 14:32 [PATCH] x86: clean up confusing x86_mask Jia Zhang
2017-12-31 11:43 ` kbuild test robot
2017-12-31 11:44 ` kbuild test robot
@ 2017-12-31 16:55 ` kbuild test robot
2 siblings, 0 replies; 4+ messages in thread
From: kbuild test robot @ 2017-12-31 16:55 UTC (permalink / raw)
To: Jia Zhang
Cc: kbuild-all, bp, mingo, hpa, tglx, tony.luck, x86, linux-kernel,
Jia Zhang
Hi Jia,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on v4.15-rc5]
[also build test WARNING on next-20171222]
[cannot apply to tip/x86/core]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jia-Zhang/x86-clean-up-confusing-x86_mask/20171231-182946
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
vim +165 drivers/char/hw_random/via-rng.c
135233635 Michael Buesch 2006-06-26 128
135233635 Michael Buesch 2006-06-26 129 static int via_rng_init(struct hwrng *rng)
135233635 Michael Buesch 2006-06-26 130 {
11025e855 Dave Jones 2008-02-06 131 struct cpuinfo_x86 *c = &cpu_data(0);
135233635 Michael Buesch 2006-06-26 132 u32 lo, hi, old_lo;
135233635 Michael Buesch 2006-06-26 133
858576bdc Harald Welte 2009-05-15 134 /* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG
858576bdc Harald Welte 2009-05-15 135 * is always enabled if CPUID rng_en is set. There is no
858576bdc Harald Welte 2009-05-15 136 * RNG configuration like it used to be the case in this
858576bdc Harald Welte 2009-05-15 137 * register */
858576bdc Harald Welte 2009-05-15 138 if ((c->x86 == 6) && (c->x86_model >= 0x0f)) {
362f924b6 Borislav Petkov 2015-12-07 139 if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) {
7a1ae9c0c Sudip Mukherjee 2014-09-15 140 pr_err(PFX "can't enable hardware RNG "
858576bdc Harald Welte 2009-05-15 141 "if XSTORE is not enabled\n");
858576bdc Harald Welte 2009-05-15 142 return -ENODEV;
858576bdc Harald Welte 2009-05-15 143 }
858576bdc Harald Welte 2009-05-15 144 return 0;
858576bdc Harald Welte 2009-05-15 145 }
858576bdc Harald Welte 2009-05-15 146
135233635 Michael Buesch 2006-06-26 147 /* Control the RNG via MSR. Tread lightly and pay very close
135233635 Michael Buesch 2006-06-26 148 * close attention to values written, as the reserved fields
135233635 Michael Buesch 2006-06-26 149 * are documented to be "undefined and unpredictable"; but it
135233635 Michael Buesch 2006-06-26 150 * does not say to write them as zero, so I make a guess that
135233635 Michael Buesch 2006-06-26 151 * we restore the values we find in the register.
135233635 Michael Buesch 2006-06-26 152 */
135233635 Michael Buesch 2006-06-26 153 rdmsr(MSR_VIA_RNG, lo, hi);
135233635 Michael Buesch 2006-06-26 154
135233635 Michael Buesch 2006-06-26 155 old_lo = lo;
135233635 Michael Buesch 2006-06-26 156 lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
135233635 Michael Buesch 2006-06-26 157 lo &= ~VIA_XSTORE_CNT_MASK;
135233635 Michael Buesch 2006-06-26 158 lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
135233635 Michael Buesch 2006-06-26 159 lo |= VIA_RNG_ENABLE;
11025e855 Dave Jones 2008-02-06 160 lo |= VIA_NOISESRC1;
11025e855 Dave Jones 2008-02-06 161
11025e855 Dave Jones 2008-02-06 162 /* Enable secondary noise source on CPUs where it is present. */
11025e855 Dave Jones 2008-02-06 163
11025e855 Dave Jones 2008-02-06 164 /* Nehemiah stepping 8 and higher */
11025e855 Dave Jones 2008-02-06 @165 if ((c->x86_model == 9) && (c->x86_mask > 7))
11025e855 Dave Jones 2008-02-06 166 lo |= VIA_NOISESRC2;
11025e855 Dave Jones 2008-02-06 167
11025e855 Dave Jones 2008-02-06 168 /* Esther */
11025e855 Dave Jones 2008-02-06 169 if (c->x86_model >= 10)
11025e855 Dave Jones 2008-02-06 170 lo |= VIA_NOISESRC2;
135233635 Michael Buesch 2006-06-26 171
135233635 Michael Buesch 2006-06-26 172 if (lo != old_lo)
135233635 Michael Buesch 2006-06-26 173 wrmsr(MSR_VIA_RNG, lo, hi);
135233635 Michael Buesch 2006-06-26 174
135233635 Michael Buesch 2006-06-26 175 /* perhaps-unnecessary sanity check; remove after testing if
135233635 Michael Buesch 2006-06-26 176 unneeded */
135233635 Michael Buesch 2006-06-26 177 rdmsr(MSR_VIA_RNG, lo, hi);
135233635 Michael Buesch 2006-06-26 178 if ((lo & VIA_RNG_ENABLE) == 0) {
7a1ae9c0c Sudip Mukherjee 2014-09-15 179 pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
135233635 Michael Buesch 2006-06-26 180 return -ENODEV;
135233635 Michael Buesch 2006-06-26 181 }
135233635 Michael Buesch 2006-06-26 182
135233635 Michael Buesch 2006-06-26 183 return 0;
135233635 Michael Buesch 2006-06-26 184 }
135233635 Michael Buesch 2006-06-26 185
:::::: The code at line 165 was first introduced by commit
:::::: 11025e855235144271a0e447e3650b203f8215f4 via-rng: enable secondary noise source on CPUs where it is present
:::::: TO: Dave Jones <davej@redhat.com>
:::::: CC: Linus Torvalds <torvalds@woody.linux-foundation.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply [flat|nested] 4+ messages in thread
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Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2017-12-29 14:32 [PATCH] x86: clean up confusing x86_mask Jia Zhang
2017-12-31 11:43 ` kbuild test robot
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2017-12-31 16:55 ` kbuild test robot
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