From: Palmer Dabbelt <palmer@sifive.com>
To: Arnd Bergmann <arnd@arndb.de>,
Christoph Hellwig <hch@infradead.org>,
linux-kernel@vger.kernel.org
Cc: patches@groups.riscv.org
Subject: Use arm64's scheme for registering first-level IRQ handlers on RISC-V
Date: Thu, 18 Jan 2018 07:40:03 -0800 [thread overview]
Message-ID: <20180118154005.24994-1-palmer@sifive.com> (raw)
This patch set has been sitting around for a while, but it got a bit lost in
the shuffle. In RISC-V land we currently couple do_IRQ (the C entry point for
interrupt handling) to our first-level interrupt controller. While this isn't
completely crazy (as the first-level interrupt controller is specified by the
ISA), it is a bit awkward.
This patch set decouples our trap handler from our first-level IRQ chip driver
by copying what a handful of other architectures are doing. This does add an
additional load to the interrupt handling path, but there's a handful of
performance problems in there that I've been meaning to look at so I don't mind
adding another one for now. The advantage is that our irqchip driver is
decoupled from our arch port, at least at compile time.
next reply other threads:[~2018-01-18 16:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-18 15:40 Palmer Dabbelt [this message]
2018-01-18 15:40 ` [PATCH 1/2] asm-generic: Add a generic set_handle_irq Palmer Dabbelt
2018-01-18 15:45 ` Christoph Hellwig
2018-01-25 3:08 ` [patches] " Palmer Dabbelt
2018-01-18 15:40 ` [PATCH 2/2] RISC-V: Move to the new asm-generic IRQ handler Palmer Dabbelt
2018-01-18 16:43 ` Use arm64's scheme for registering first-level IRQ handlers on RISC-V Arnd Bergmann
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