From: Peter Zijlstra <peterz@infradead.org>
To: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Luwei Kang <luwei.kang@intel.com>,
kvm@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com,
hpa@zytor.com, x86@kernel.org, chao.p.peng@linux.intel.com,
thomas.lendacky@amd.com, bp@suse.de, Kan.liang@intel.com,
Janakarajan.Natarajan@amd.com, dwmw@amazon.co.uk,
linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
kstewart@linuxfoundation.org, gregkh@linuxfoundation.org,
pbonzini@redhat.com, rkrcmar@redhat.com, david@redhat.com,
bsd@redhat.com, yu.c.zhang@linux.intel.com, joro@8bytes.org
Subject: Re: [PATCH v9 04/12] perf/x86/intel/pt: add new capability for Intel PT
Date: Thu, 7 Jun 2018 15:51:03 +0200 [thread overview]
Message-ID: <20180607135103.GN12198@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20180607134051.rwu5pqtz45cgq7ve@um.fi.intel.com>
On Thu, Jun 07, 2018 at 04:40:51PM +0300, Alexander Shishkin wrote:
> On Tue, May 22, 2018 at 12:52:07PM +0800, Luwei Kang wrote:
> > CPUID(EAX=14H,ECX=0):EBX[bit 3] = 1 indicates support of
> > output to Trace Transport subsystem.
> > MSR IA32_RTIT_CTL.FabricEn[bit 6] is reserved if
> > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0.
>
> This should instead say:
>
> This adds support for "output to Trace Transport subsystem" capability
> of Intel PT, as documented in IA SDM Chapter 36.x.y.z. It means that
> PT can output its trace to an MMIO address range rather than system
> memory buffer.
The $subject also needs attention.
next prev parent reply other threads:[~2018-06-07 13:51 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-22 4:52 [PATCH v9 00/12] Intel Processor Trace virtualization enabling Luwei Kang
2018-05-22 4:52 ` [PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Luwei Kang
2018-06-07 6:50 ` Kang, Luwei
2018-06-07 11:21 ` Paolo Bonzini
2018-05-22 4:52 ` [PATCH v9 02/12] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2018-05-22 4:52 ` [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Luwei Kang
2018-06-07 13:33 ` Alexander Shishkin
2018-06-08 14:26 ` Kang, Luwei
2018-05-22 4:52 ` [PATCH v9 04/12] perf/x86/intel/pt: add new capability for Intel PT Luwei Kang
2018-06-07 13:40 ` Alexander Shishkin
2018-06-07 13:51 ` Peter Zijlstra [this message]
2018-06-08 14:37 ` Kang, Luwei
2018-06-08 14:34 ` Kang, Luwei
2018-05-22 4:52 ` [PATCH v9 05/12] perf/x86/intel/pt: Introduce a new function to get capability of " Luwei Kang
2018-05-22 4:52 ` [PATCH v9 06/12] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-06-07 13:26 ` Alexander Shishkin
2018-06-08 14:19 ` Kang, Luwei
2018-06-11 11:39 ` Paolo Bonzini
2018-05-22 4:52 ` [PATCH v9 07/12] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-05-22 4:52 ` [PATCH v9 08/12] KVM: x86: Add Intel Processor Trace context switch for each vcpu Luwei Kang
2018-05-22 4:52 ` [PATCH v9 09/12] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-06-07 13:56 ` Alexander Shishkin
2018-06-08 14:56 ` Kang, Luwei
2018-06-11 11:41 ` Paolo Bonzini
2018-06-12 1:30 ` Kang, Luwei
2018-05-22 4:52 ` [PATCH v9 10/12] KVM: x86: Implement Intel Processor Trace MSRs read/write emulation Luwei Kang
2018-06-07 14:12 ` Alexander Shishkin
2018-06-08 15:12 ` Kang, Luwei
2018-05-22 4:52 ` [PATCH v9 11/12] KVM: x86: Set intercept for Intel PT MSRs read/write Luwei Kang
2018-06-07 14:22 ` Alexander Shishkin
2018-06-08 15:16 ` Kang, Luwei
2018-05-22 4:52 ` [PATCH v9 12/12] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
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