[PATCH linux-next v2 0/6] clk: renesas: adg: add AVB Clock

[PATCH linux-next v2 0/6] clk: renesas: adg: add AVB Clock

[jiada_wang]

From: Jiada Wang <jiada_wang@mentor.com>

on R-Car SoCs there are AVB Counter Clocks, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.

This patch-set adds 'adg' clock to R-Car Soc, and changes adg driver to
register avb clocks when clock-cells of rcar_sound node is 2.

---
v2:
- expends adg register size and register avb clocks instead of
  add new clk-avb driver
- Add adg clock 

v1: initial version

Jiada Wang (2):
  dt-bindings: clock: add clock id for renesas adg clocks
  ASoC: rsnd: add avb clocks

Takeshi Kihara (4):
  clk: renesas: r8a7795: Add ADG clock
  clk: renesas: r8a7796: Add ADG clock
  clk: renesas: r8a77990: Add ADG clocks
  clk: renesas: r8a77995: Add ADG clock

 drivers/clk/renesas/r8a7795-cpg-mssr.c  |   1 +
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |   1 +
 drivers/clk/renesas/r8a77990-cpg-mssr.c |   1 +
 drivers/clk/renesas/r8a77995-cpg-mssr.c |   1 +
 include/dt-bindings/clock/renesas-adg.h |  11 +
 sound/soc/sh/rcar/adg.c                 | 306 +++++++++++++++++++++++-
 sound/soc/sh/rcar/gen.c                 |   9 +
 sound/soc/sh/rcar/rsnd.h                |   9 +
 8 files changed, 330 insertions(+), 9 deletions(-)
 create mode 100644 include/dt-bindings/clock/renesas-adg.h

-- 
2.17.0

[PATCH linux-next v2 1/6] clk: renesas: r8a7795: Add ADG clock

[jiada_wang]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds ADG clock to the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
---
 drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 119c02440726..813288099c84 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -237,6 +237,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
 	DEF_MOD("can-if0",		 916,	R8A7795_CLK_S3D4),
 	DEF_MOD("i2c6",			 918,	R8A7795_CLK_S0D6),
 	DEF_MOD("i2c5",			 919,	R8A7795_CLK_S0D6),
+	DEF_MOD("adg",			 922,	R8A7795_CLK_S0D1),
 	DEF_MOD("i2c-dvfs",		 926,	R8A7795_CLK_CP),
 	DEF_MOD("i2c4",			 927,	R8A7795_CLK_S0D6),
 	DEF_MOD("i2c3",			 928,	R8A7795_CLK_S0D6),
-- 
2.17.0

[PATCH linux-next v2 2/6] clk: renesas: r8a7796: Add ADG clock

[jiada_wang]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds ADG clock to the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
---
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 10567386e6dd..7568204e9ed6 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -209,6 +209,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
 	DEF_MOD("can-if0",		 916,	R8A7796_CLK_S3D4),
 	DEF_MOD("i2c6",			 918,	R8A7796_CLK_S0D6),
 	DEF_MOD("i2c5",			 919,	R8A7796_CLK_S0D6),
+	DEF_MOD("adg",			 922,	R8A7796_CLK_S0D1),
 	DEF_MOD("i2c-dvfs",		 926,	R8A7796_CLK_CP),
 	DEF_MOD("i2c4",			 927,	R8A7796_CLK_S0D6),
 	DEF_MOD("i2c3",			 928,	R8A7796_CLK_S0D6),
-- 
2.17.0

[PATCH linux-next v2 3/6] clk: renesas: r8a77990: Add ADG clocks

[jiada_wang]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds ADG clock to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
---
 drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9eb80180eea0..3bb55037a9e3 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -203,6 +203,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
 	DEF_MOD("can-if0",		 916,	R8A77990_CLK_S3D4),
 	DEF_MOD("i2c6",			 918,	R8A77990_CLK_S3D2),
 	DEF_MOD("i2c5",			 919,	R8A77990_CLK_S3D2),
+	DEF_MOD("adg",			 922,	R8A77990_CLK_ZA8),
 	DEF_MOD("i2c-dvfs",		 926,	R8A77990_CLK_CP),
 	DEF_MOD("i2c4",			 927,	R8A77990_CLK_S3D2),
 	DEF_MOD("i2c3",			 928,	R8A77990_CLK_S3D2),
-- 
2.17.0

[PATCH linux-next v2 4/6] clk: renesas: r8a77995: Add ADG clock

[jiada_wang]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds ADG clock to the R8A77995 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
---
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 47e60e3dbe05..933084d896e3 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -165,6 +165,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
 	DEF_MOD("can-fd",		 914,	R8A77995_CLK_S3D2),
 	DEF_MOD("can-if1",		 915,	R8A77995_CLK_S3D4),
 	DEF_MOD("can-if0",		 916,	R8A77995_CLK_S3D4),
+	DEF_MOD("adg",			 922,   R8A77995_CLK_ZA8),
 	DEF_MOD("i2c3",			 928,	R8A77995_CLK_S3D2),
 	DEF_MOD("i2c2",			 929,	R8A77995_CLK_S3D2),
 	DEF_MOD("i2c1",			 930,	R8A77995_CLK_S3D2),
-- 
2.17.0

Re: [PATCH linux-next v2 0/6] clk: renesas: adg: add AVB Clock

[Vladimir Zapolskiy]

Hi Jiada,

On 12/03/2018 01:21 PM, jiada_wang@mentor.com wrote:
> From: Jiada Wang <jiada_wang@mentor.com>
> 
> on R-Car SoCs there are AVB Counter Clocks, each clock has 12bits integral
> and 8 bits fractional dividers which operates with S0D1ϕ clock.
> 
> This patch-set adds 'adg' clock to R-Car Soc, and changes adg driver to
> register avb clocks when clock-cells of rcar_sound node is 2.
> 
> ---
> v2:
> - expends adg register size and register avb clocks instead of
>   add new clk-avb driver
> - Add adg clock 
> 
> v1: initial version
> 
> Jiada Wang (2):
>   dt-bindings: clock: add clock id for renesas adg clocks
>   ASoC: rsnd: add avb clocks
> 
> Takeshi Kihara (4):
>   clk: renesas: r8a7795: Add ADG clock
>   clk: renesas: r8a7796: Add ADG clock
>   clk: renesas: r8a77990: Add ADG clocks
>   clk: renesas: r8a77995: Add ADG clock
> 

plural 'clocks' for r8a77990 vs. 'clock' in other cases, please unify subjects.

You can consider to add the ADG clock description for r8a77965 / M3-N as well.

>  drivers/clk/renesas/r8a7795-cpg-mssr.c  |   1 +
>  drivers/clk/renesas/r8a7796-cpg-mssr.c  |   1 +
>  drivers/clk/renesas/r8a77990-cpg-mssr.c |   1 +
>  drivers/clk/renesas/r8a77995-cpg-mssr.c |   1 +
>  include/dt-bindings/clock/renesas-adg.h |  11 +

The new header file added above is not needed in my opinion.

>  sound/soc/sh/rcar/adg.c                 | 306 +++++++++++++++++++++++-
>  sound/soc/sh/rcar/gen.c                 |   9 +
>  sound/soc/sh/rcar/rsnd.h                |   9 +
>  8 files changed, 330 insertions(+), 9 deletions(-)
>  create mode 100644 include/dt-bindings/clock/renesas-adg.h
> 

--
Best wishes,
Vladimir

Re: [PATCH linux-next v2 0/6] clk: renesas: adg: add AVB Clock

[Jiada Wang]

Hi Vladimir

Thanks for your comments

On 2018/12/03 21:11, Vladimir Zapolskiy wrote:
> Hi Jiada,
>
> On 12/03/2018 01:21 PM, jiada_wang@mentor.com wrote:
>> From: Jiada Wang <jiada_wang@mentor.com>
>>
>> on R-Car SoCs there are AVB Counter Clocks, each clock has 12bits integral
>> and 8 bits fractional dividers which operates with S0D1ϕ clock.
>>
>> This patch-set adds 'adg' clock to R-Car Soc, and changes adg driver to
>> register avb clocks when clock-cells of rcar_sound node is 2.
>>
>> ---
>> v2:
>> - expends adg register size and register avb clocks instead of
>>    add new clk-avb driver
>> - Add adg clock
>>
>> v1: initial version
>>
>> Jiada Wang (2):
>>    dt-bindings: clock: add clock id for renesas adg clocks
>>    ASoC: rsnd: add avb clocks
>>
>> Takeshi Kihara (4):
>>    clk: renesas: r8a7795: Add ADG clock
>>    clk: renesas: r8a7796: Add ADG clock
>>    clk: renesas: r8a77990: Add ADG clocks
>>    clk: renesas: r8a77995: Add ADG clock
>>
> plural 'clocks' for r8a77990 vs. 'clock' in other cases, please unify subjects.
>
> You can consider to add the ADG clock description for r8a77965 / M3-N as well.
will unify the subjects and add ADG clock to r8a77965 in next version
>>   drivers/clk/renesas/r8a7795-cpg-mssr.c  |   1 +
>>   drivers/clk/renesas/r8a7796-cpg-mssr.c  |   1 +
>>   drivers/clk/renesas/r8a77990-cpg-mssr.c |   1 +
>>   drivers/clk/renesas/r8a77995-cpg-mssr.c |   1 +
>>   include/dt-bindings/clock/renesas-adg.h |  11 +
> The new header file added above is not needed in my opinion.
>
>>   sound/soc/sh/rcar/adg.c                 | 306 +++++++++++++++++++++++-
>>   sound/soc/sh/rcar/gen.c                 |   9 +
>>   sound/soc/sh/rcar/rsnd.h                |   9 +
>>   8 files changed, 330 insertions(+), 9 deletions(-)
>>   create mode 100644 include/dt-bindings/clock/renesas-adg.h
>>
> --
> Best wishes,
> Vladimir