From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Andy Lutomirski <luto@kernel.org>,
Josh Poimboeuf <jpoimboe@redhat.com>
Subject: [patch 06/14] x86/exceptions: Add structs for exception stacks
Date: Sun, 31 Mar 2019 23:40:26 +0200 [thread overview]
Message-ID: <20190331215135.313058385@linutronix.de> (raw)
In-Reply-To: <20190331214020.836098943@linutronix.de>
At the moment everything assumes a full linear mapping of the various
exception stacks. Adding guard pages to the cpu entry area mapping of the
exception stacks will break that assumption.
As a preparatory step convert both the real storage and the effective
mapping in the cpu entry area from character arrays to structures.
To ensure that both arrays have the same ordering and the same size of the
individual stacks fill the members with a macro. The guard size is the only
difference between the two resulting structures. For now both have guard
size 0 until the preparation of all usage sites is done.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/cpu_entry_area.h | 35 +++++++++++++++++++++++++++++-----
arch/x86/kernel/cpu/common.c | 2 -
arch/x86/mm/cpu_entry_area.c | 8 ++-----
3 files changed, 34 insertions(+), 11 deletions(-)
--- a/arch/x86/include/asm/cpu_entry_area.h
+++ b/arch/x86/include/asm/cpu_entry_area.h
@@ -7,6 +7,34 @@
#include <asm/processor.h>
#include <asm/intel_ds.h>
+#ifdef CONFIG_X86_64
+
+/* Macro to enforce the same ordering and stack sizes */
+#define ESTACKS_MEMBERS(guardsize) \
+ char DF_stack[EXCEPTION_STKSZ]; \
+ char DF_stack_guard[guardsize]; \
+ char NMI_stack[EXCEPTION_STKSZ]; \
+ char NMI_stack_guard[guardsize]; \
+ char DB_stack[DEBUG_STKSZ]; \
+ char DB_stack_guard[guardsize]; \
+ char MCE_stack[EXCEPTION_STKSZ]; \
+ char MCE_stack_guard[guardsize]; \
+
+/* The exception stacks linear storage. No guard pages required */
+struct exception_stacks {
+ ESTACKS_MEMBERS(0)
+};
+
+/*
+ * The effective cpu entry area mapping with guard pages. Guard size is
+ * zero until the code which makes assumptions about linear mapping is
+ * cleaned up.
+ */
+struct cea_exception_stacks {
+ ESTACKS_MEMBERS(0)
+};
+#endif
+
/*
* cpu_entry_area is a percpu region that contains things needed by the CPU
* and early entry/exit code. Real types aren't used for all fields here
@@ -32,12 +60,9 @@ struct cpu_entry_area {
#ifdef CONFIG_X86_64
/*
- * Exception stacks used for IST entries.
- *
- * In the future, this should have a separate slot for each stack
- * with guard pages between them.
+ * Exception stacks used for IST entries with guard pages.
*/
- char exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ];
+ struct cea_exception_stacks estacks;
#endif
#ifdef CONFIG_CPU_SUP_INTEL
/*
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1754,7 +1754,7 @@ void cpu_init(void)
* set up and load the per-CPU TSS
*/
if (!oist->ist[0]) {
- char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
+ char *estacks = (char *)&get_cpu_entry_area(cpu)->estacks;
for (v = 0; v < N_EXCEPTION_STACKS; v++) {
estacks += exception_stack_sizes[v];
--- a/arch/x86/mm/cpu_entry_area.c
+++ b/arch/x86/mm/cpu_entry_area.c
@@ -13,8 +13,7 @@
static DEFINE_PER_CPU_PAGE_ALIGNED(struct entry_stack_page, entry_stack_storage);
#ifdef CONFIG_X86_64
-static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
- [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
+static DEFINE_PER_CPU_PAGE_ALIGNED(struct exception_stacks, exception_stacks);
#endif
struct cpu_entry_area *get_cpu_entry_area(int cpu)
@@ -138,9 +137,8 @@ static void __init setup_cpu_entry_area(
#ifdef CONFIG_X86_64
BUILD_BUG_ON(sizeof(exception_stacks) % PAGE_SIZE != 0);
BUILD_BUG_ON(sizeof(exception_stacks) !=
- sizeof(((struct cpu_entry_area *)0)->exception_stacks));
- cea_map_percpu_pages(&cea->exception_stacks,
- &per_cpu(exception_stacks, cpu),
+ sizeof(((struct cpu_entry_area *)0)->estacks));
+ cea_map_percpu_pages(&cea->estacks, &per_cpu(exception_stacks, cpu),
sizeof(exception_stacks) / PAGE_SIZE, PAGE_KERNEL);
#endif
percpu_setup_debug_store(cpu);
next prev parent reply other threads:[~2019-03-31 22:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-31 21:40 [patch 00/14] x86/exceptions: Add guard patches to IST stacks Thomas Gleixner
2019-03-31 21:40 ` [patch 01/14] x86/irq/64: Limit IST stack overflow check to #DB stack Thomas Gleixner
2019-04-01 18:03 ` Borislav Petkov
2019-04-02 16:34 ` Sean Christopherson
2019-03-31 21:40 ` [patch 02/14] x86/idt: Remove unused macro SISTG Thomas Gleixner
2019-04-01 4:04 ` Andy Lutomirski
2019-03-31 21:40 ` [patch 03/14] x86/exceptions: Remove unused stack defines on 32bit Thomas Gleixner
2019-03-31 21:40 ` [patch 04/14] x86/exceptions: Make IST index zero based Thomas Gleixner
2019-04-01 7:30 ` Peter Zijlstra
2019-04-01 7:33 ` Thomas Gleixner
2019-04-02 16:49 ` Sean Christopherson
2019-04-03 16:35 ` Borislav Petkov
2019-03-31 21:40 ` [patch 05/14] x86/cpu_entry_area: Cleanup setup functions Thomas Gleixner
2019-03-31 21:40 ` Thomas Gleixner [this message]
2019-03-31 21:40 ` [patch 07/14] x86/cpu_entry_area: Prepare for IST guard pages Thomas Gleixner
2019-03-31 21:40 ` [patch 08/14] x86/cpu_entry_area: Provide exception stack accessor Thomas Gleixner
2019-03-31 21:40 ` [patch 09/14] x86/traps: Use cpu_entry_area instead of orig_ist Thomas Gleixner
2019-03-31 21:40 ` [patch 10/14] x86/irq/64: Use cpu entry area " Thomas Gleixner
2019-03-31 21:40 ` [patch 11/14] x86/dumpstack/64: Use cpu_entry_area " Thomas Gleixner
2019-03-31 21:40 ` [patch 12/14] x86/cpu: Prepare TSS.IST setup for guard pages Thomas Gleixner
2019-04-02 16:57 ` Sean Christopherson
2019-03-31 21:40 ` [patch 13/14] x86/cpu: Remove orig_ist array Thomas Gleixner
2019-03-31 21:40 ` [patch 14/14] x86/exceptions: Enable IST guard pages Thomas Gleixner
2019-04-02 10:19 ` [patch 15/14] x86/dumpstack/64: Speedup in_exception_stack() Thomas Gleixner
2019-04-02 15:43 ` Josh Poimboeuf
2019-04-02 15:48 ` Thomas Gleixner
2019-04-02 15:51 ` Josh Poimboeuf
2019-04-02 15:53 ` Josh Poimboeuf
2019-04-03 8:08 ` Peter Zijlstra
2019-04-03 8:10 ` Peter Zijlstra
2019-04-03 15:11 ` Josh Poimboeuf
2019-04-02 16:11 ` Andy Lutomirski
2019-04-02 18:27 ` Thomas Gleixner
2019-04-02 19:29 ` Thomas Gleixner
2019-04-03 0:36 ` Andy Lutomirski
2019-04-03 16:26 ` Thomas Gleixner
2019-04-03 19:42 ` Thomas Gleixner
2019-04-04 0:03 ` Andy Lutomirski
2019-04-02 19:02 ` Rasmus Villemoes
2019-04-02 19:21 ` Thomas Gleixner
2019-04-03 8:02 ` Peter Zijlstra
2019-04-01 4:03 ` [patch 00/14] x86/exceptions: Add guard patches to IST stacks Andy Lutomirski
2019-04-03 16:30 ` Thomas Gleixner
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