* Re: [PATCH] x86/split_lock: Add Icelake microserver CPU model
2020-04-30 23:46 [PATCH] x86/split_lock: Add Icelake microserver CPU model Fenghua Yu
@ 2020-05-14 16:55 ` Fenghua Yu
2020-05-14 18:35 ` [tip: x86/splitlock] " tip-bot2 for Fenghua Yu
2020-05-28 19:12 ` [tip: x86/splitlock] x86/split_lock: Add Icelake microserver and Tigerlake CPU models tip-bot2 for Fenghua Yu
2 siblings, 0 replies; 4+ messages in thread
From: Fenghua Yu @ 2020-05-14 16:55 UTC (permalink / raw)
To: Thomas Gleixner, Peter Zijlstra, Borislav Petkov, Ingo Molnar, Tony Luck
Cc: x86, linux-kernel
On Thu, Apr 30, 2020 at 04:46:35PM -0700, Fenghua Yu wrote:
> Icelake microserver CPU supports split lock detection while it doesn't
> have the split lock enumeration bit in IA32_CORE_CAPABILITIES.
>
> Enumerate the feature by model number.
>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> ---
> arch/x86/kernel/cpu/intel.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index a19a680542ce..b59bc4ab2425 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -1135,6 +1135,7 @@ void switch_to_sld(unsigned long tifn)
> static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
> X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
> X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
> + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
> X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
> X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
> X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
Hi, Thomas,
Any comment on this patch? Will you accept this patch?
Thanks.
-Fenghua
^ permalink raw reply [flat|nested] 4+ messages in thread* [tip: x86/splitlock] x86/split_lock: Add Icelake microserver CPU model
2020-04-30 23:46 [PATCH] x86/split_lock: Add Icelake microserver CPU model Fenghua Yu
2020-05-14 16:55 ` Fenghua Yu
@ 2020-05-14 18:35 ` tip-bot2 for Fenghua Yu
2020-05-28 19:12 ` [tip: x86/splitlock] x86/split_lock: Add Icelake microserver and Tigerlake CPU models tip-bot2 for Fenghua Yu
2 siblings, 0 replies; 4+ messages in thread
From: tip-bot2 for Fenghua Yu @ 2020-05-14 18:35 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Fenghua Yu, Borislav Petkov, Tony Luck, x86, LKML
The following commit has been merged into the x86/splitlock branch of tip:
Commit-ID: 0ed7bf1d92eafc37bb9eb7c8692a8e44d24f9b99
Gitweb: https://git.kernel.org/tip/0ed7bf1d92eafc37bb9eb7c8692a8e44d24f9b99
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Thu, 30 Apr 2020 16:46:35 -07:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Thu, 14 May 2020 19:25:10 +02:00
x86/split_lock: Add Icelake microserver CPU model
Icelake microserver CPU supports split lock detection while it doesn't
have the split lock enumeration bit in IA32_CORE_CAPABILITIES.
Enumerate the feature by model number.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/1588290395-2677-1-git-send-email-fenghua.yu@intel.com
---
arch/x86/kernel/cpu/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index a19a680..b59bc4a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -1135,6 +1135,7 @@ void switch_to_sld(unsigned long tifn)
static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
^ permalink raw reply [flat|nested] 4+ messages in thread* [tip: x86/splitlock] x86/split_lock: Add Icelake microserver and Tigerlake CPU models
2020-04-30 23:46 [PATCH] x86/split_lock: Add Icelake microserver CPU model Fenghua Yu
2020-05-14 16:55 ` Fenghua Yu
2020-05-14 18:35 ` [tip: x86/splitlock] " tip-bot2 for Fenghua Yu
@ 2020-05-28 19:12 ` tip-bot2 for Fenghua Yu
2 siblings, 0 replies; 4+ messages in thread
From: tip-bot2 for Fenghua Yu @ 2020-05-28 19:12 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Fenghua Yu, Borislav Petkov, Tony Luck, x86, LKML
The following commit has been merged into the x86/splitlock branch of tip:
Commit-ID: 429ac8b75a0b1c3478ffd584de8a63075cbe25e7
Gitweb: https://git.kernel.org/tip/429ac8b75a0b1c3478ffd584de8a63075cbe25e7
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Thu, 30 Apr 2020 16:46:35 -07:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Thu, 28 May 2020 21:06:42 +02:00
x86/split_lock: Add Icelake microserver and Tigerlake CPU models
Icelake microserver CPU supports split lock detection while it doesn't
have the split lock enumeration bit in IA32_CORE_CAPABILITIES. Tigerlake
CPUs do enumerate the MSR.
[ bp: Merge the two model-adding patches into one. ]
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/1588290395-2677-1-git-send-email-fenghua.yu@intel.com
---
arch/x86/kernel/cpu/intel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index a19a680..6abbcc7 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -1135,9 +1135,12 @@ void switch_to_sld(unsigned long tifn)
static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1),
{}
};
^ permalink raw reply [flat|nested] 4+ messages in thread