From: Lucas Tanure <tanureal@opensource.cirrus.com>
To: Mark Brown <broonie@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Sanjay R Mehta <sanju.mehta@amd.com>,
Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@amd.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<patches@opensource.cirrus.com>,
Lucas Tanure <tanureal@opensource.cirrus.com>
Subject: [PATCH 2/9] spi: core: Add flag for controllers that can't hold cs between transfers
Date: Tue, 24 Aug 2021 11:40:34 +0100 [thread overview]
Message-ID: <20210824104041.708945-3-tanureal@opensource.cirrus.com> (raw)
In-Reply-To: <20210824104041.708945-1-tanureal@opensource.cirrus.com>
Create a flag for a controller that has an automatic cs selection and
can't hold cs activated between transfers
Some messages send address and data split between two transfers, see
regmap-spi, and without the cs held the data loses it`s meaning
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
---
include/linux/spi/spi.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8371bca13729..f5b55c237634 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -514,6 +514,7 @@ struct spi_controller {
#define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */
#define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
+#define SPI_CONTROLLER_CS_PER_TRANSFER BIT(6) /* SPI controller can not hold CS between transfers */
/* flag indicating if the allocation of this struct is devres-managed */
bool devm_allocated;
--
2.33.0
next prev parent reply other threads:[~2021-08-24 10:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-24 10:40 [PATCH 0/9] Improve support for AMD SPI controllers Lucas Tanure
2021-08-24 10:40 ` [PATCH 1/9] regmap: spi: Set regmap max raw r/w from max_transfer_size Lucas Tanure
2021-08-24 16:42 ` Mark Brown
2021-08-24 10:40 ` Lucas Tanure [this message]
2021-08-24 16:38 ` [PATCH 2/9] spi: core: Add flag for controllers that can't hold cs between transfers Mark Brown
2021-08-24 10:40 ` [PATCH 3/9] regmap: spi: SPI_CONTROLLER_CS_PER_TRANSFER affects max read/write Lucas Tanure
2021-08-24 16:37 ` Mark Brown
2021-08-25 17:13 ` Lucas tanure
2021-08-25 17:21 ` Mark Brown
2021-08-24 10:40 ` [PATCH 4/9] spi: amd: Refactor code to use less spi_master_get_devdata Lucas Tanure
2021-08-24 10:40 ` [PATCH 5/9] spi: amd: Refactor amd_spi_busy_wait to use readl_poll_timeout Lucas Tanure
2021-08-24 16:46 ` Mark Brown
2021-08-24 10:40 ` [PATCH 6/9] spi: amd: Remove uneeded variable Lucas Tanure
2021-08-24 10:40 ` [PATCH 7/9] spi: amd: Check for idle bus before execute opcode Lucas Tanure
2021-08-24 16:49 ` Mark Brown
2021-08-24 10:40 ` [PATCH 8/9] spi: amd: Refactor to overcome 70 bytes per CS limitation Lucas Tanure
2021-08-24 17:16 ` Mark Brown
2021-08-24 17:18 ` Mark Brown
2021-08-24 10:40 ` [PATCH 9/9] spi: amd: Add support for latest platform Lucas Tanure
2021-08-24 15:44 ` kernel test robot
2021-08-24 17:19 ` Mark Brown
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