From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Rob Herring <robh@kernel.org>, Ondrej Jirman <megous@megous.com>,
Icenowy Zheng <icenowy@aosc.io>,
Samuel Holland <samuel@sholland.org>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v10 16/18] arm64: dts: allwinner: h616: Add USB nodes
Date: Fri, 11 Feb 2022 12:26:41 +0000 [thread overview]
Message-ID: <20220211122643.1343315-17-andre.przywara@arm.com> (raw)
In-Reply-To: <20220211122643.1343315-1-andre.przywara@arm.com>
Add the nodes for the MUSB and the four USB host controllers to the SoC
.dtsi, along with the PHY node needed to bind all of them together.
EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
some quirks (handled in the driver).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index cc06cdd15ba5..bf27ad1890cb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -486,6 +486,166 @@ mdio0: mdio {
};
};
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+ reg = <0x05100000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@5100400 {
+ compatible = "allwinner,sun50i-h616-usb-phy";
+ reg = <0x05100400 0x24>,
+ <0x05101800 0x14>,
+ <0x05200800 0x14>,
+ <0x05310800 0x14>,
+ <0x05311800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>,
+ <&ccu CLK_BUS_EHCI2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy",
+ "pmu2_clk";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@5200000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05200000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@5200400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05200400 0x100>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@5310000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05310000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_BUS_EHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>,
+ <&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@5310400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05310400 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@5311000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05311000 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_BUS_EHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>,
+ <&ccu RST_BUS_EHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@5311400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05311400 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
--
2.25.1
next prev parent reply other threads:[~2022-02-11 12:27 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 12:26 [PATCH v10 00/18] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2022-02-11 12:26 ` [PATCH v10 01/18] clk: sunxi-ng: h616-r: Add RTC gate clock Andre Przywara
2022-02-23 3:22 ` Samuel Holland
2022-04-24 23:36 ` Andre Przywara
2022-04-25 0:05 ` Samuel Holland
2022-04-27 19:24 ` Andre Przywara
2022-02-11 12:26 ` [PATCH v10 02/18] clk: sunxi-ng: h616: Add PLL derived 32KHz clock Andre Przywara
2022-02-23 3:28 ` Samuel Holland
2022-02-11 12:26 ` [PATCH v10 03/18] rtc: sun6i: Fix time overflow handling Andre Przywara
2022-02-22 10:58 ` Andre Przywara
2022-03-08 21:21 ` (subset) " Alexandre Belloni
2022-02-11 12:26 ` [PATCH v10 04/18] rtc: sun6i: Add support for linear day storage Andre Przywara
2022-03-08 21:28 ` (subset) " Alexandre Belloni
2022-02-11 12:26 ` [PATCH v10 05/18] rtc: sun6i: Add support for broken-down alarm registers Andre Przywara
2022-03-08 21:28 ` (subset) " Alexandre Belloni
2022-02-11 12:26 ` [PATCH v10 06/18] rtc: sun6i: Add Allwinner H616 support Andre Przywara
2022-03-08 21:28 ` (subset) " Alexandre Belloni
2022-02-11 12:26 ` [PATCH v10 07/18] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2022-02-11 12:26 ` [PATCH v10 08/18] dt-bindings: arm: sunxi: Add two H616 board compatible strings Andre Przywara
2022-02-23 3:38 ` Samuel Holland
2022-02-11 12:26 ` [PATCH v10 09/18] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Andre Przywara
2022-02-11 12:26 ` [PATCH v10 10/18] arm64: dts: allwinner: h616: Add X96 Mate TV box support Andre Przywara
2022-02-11 12:26 ` [PATCH v10 11/18] dt-bindings: usb: Add H616 compatible string Andre Przywara
2022-02-17 23:38 ` Rob Herring
2022-02-11 12:26 ` [PATCH v10 12/18] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Andre Przywara
2022-02-23 3:42 ` Samuel Holland
2022-02-11 12:26 ` [PATCH v10 13/18] phy: sun4i-usb: Allow reset line to be shared Andre Przywara
2022-02-23 3:44 ` Samuel Holland
2022-02-23 3:50 ` Samuel Holland
2022-02-11 12:26 ` [PATCH v10 14/18] phy: sun4i-usb: Introduce port2 SIDDQ quirk Andre Przywara
2022-02-23 3:57 ` Samuel Holland
2022-02-11 12:26 ` [PATCH v10 15/18] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara
2022-02-23 3:58 ` Samuel Holland
2022-02-11 12:26 ` Andre Przywara [this message]
2022-02-11 12:26 ` [PATCH v10 17/18] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes Andre Przywara
2022-02-11 12:26 ` [PATCH v10 18/18] arm64: dts: allwinner: h616: X96 Mate: " Andre Przywara
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