* [PATCH 01/17] arm64: dts: mt8192: Add power domains controller
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 02/17] arm64: dts: mt8192: add pwrap node Allen-KH Cheng
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add power domains controller node for SoC mt8192.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c1d4030e7e4b..f10a9c75b20c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/power/mt8192-power.h>
/ {
compatible = "mediatek,mt8192";
@@ -301,6 +302,206 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8192-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ power-domain@MT8192_POWER_DOMAIN_AUDIO {
+ reg = <MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&infracfg CLK_INFRA_AUDIO>;
+ clock-names = "audio", "audio1", "audio2";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CONN {
+ reg = <MT8192_POWER_DOMAIN_CONN>;
+ clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
+ clock-names = "conn";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
+ reg = <MT8192_POWER_DOMAIN_MFG0>;
+ clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG1 {
+ reg = <MT8192_POWER_DOMAIN_MFG1>;
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_MFG2 {
+ reg = <MT8192_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG3 {
+ reg = <MT8192_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG4 {
+ reg = <MT8192_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG5 {
+ reg = <MT8192_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MFG6 {
+ reg = <MT8192_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_DISP {
+ reg = <MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&topckgen CLK_TOP_DISP_SEL>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "disp", "disp-0", "disp-1", "disp-2",
+ "disp-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_IPE {
+ reg = <MT8192_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE_SEL>,
+ <&ipesys CLK_IPE_LARB19>,
+ <&ipesys CLK_IPE_LARB20>,
+ <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_GALS>;
+ clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
+ "ipe-3";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP {
+ reg = <MT8192_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_IMG1_SEL>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "isp", "isp-0", "isp-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_ISP2 {
+ reg = <MT8192_POWER_DOMAIN_ISP2>;
+ clocks = <&topckgen CLK_TOP_IMG2_SEL>,
+ <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_GALS>;
+ clock-names = "isp2", "isp2-0", "isp2-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_MDP {
+ reg = <MT8192_POWER_DOMAIN_MDP>;
+ clocks = <&topckgen CLK_TOP_MDP_SEL>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "mdp", "mdp-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VENC {
+ reg = <MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc", "venc-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC {
+ reg = <MT8192_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_VDEC2 {
+ reg = <MT8192_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec2-0", "vdec2-1",
+ "vdec2-2";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM {
+ reg = <MT8192_POWER_DOMAIN_CAM>;
+ clocks = <&topckgen CLK_TOP_CAM_SEL>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CCU_GALS>,
+ <&camsys CLK_CAM_CAM2MM_GALS>;
+ clock-names = "cam", "cam-0", "cam-1", "cam-2",
+ "cam-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "cam_rawa-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "cam_rawb-0";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
+ clock-names = "cam_rawc-0";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8192-wdt";
reg = <0 0x10007000 0 0x100>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 02/17] arm64: dts: mt8192: add pwrap node
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 01/17] arm64: dts: mt8192: Add power domains controller Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 03/17] arm64: dts: mt8192: add spmi node Allen-KH Cheng
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add pwrap node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f10a9c75b20c..f58a13b10916 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
clock-names = "clk13m";
};
+ pwrap: pwrap@10026000 {
+ compatible = "mediatek,mt6873-pwrap";
+ reg = <0 0x10026000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 03/17] arm64: dts: mt8192: add spmi node
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 01/17] arm64: dts: mt8192: Add power domains controller Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 02/17] arm64: dts: mt8192: add pwrap node Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 04/17] arm64: dts: mt8192: Add gce node Allen-KH Cheng
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add spmi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f58a13b10916..8635c8a53472 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt6873-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST_SEL>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 04/17] arm64: dts: mt8192: Add gce node
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
` (2 preceding siblings ...)
2022-02-17 13:40 ` [PATCH 03/17] arm64: dts: mt8192: add spmi node Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 05/17] arm64: dts: mt8192: Add SCP node Allen-KH Cheng
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add gce node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 8635c8a53472..c432711a318d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -552,6 +552,15 @@
#size-cells = <0>;
};
+ gce: mailbox@10228000 {
+ compatible = "mediatek,mt8192-gce";
+ reg = <0 0x10228000 0 0x4000>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 05/17] arm64: dts: mt8192: Add SCP node
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
` (3 preceding siblings ...)
2022-02-17 13:40 ` [PATCH 04/17] arm64: dts: mt8192: Add gce node Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 06/17] arm64: dts: mt8192: Add xhci node Allen-KH Cheng
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add SCP node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c432711a318d..9d9bb67bc65d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -705,6 +705,18 @@
status = "disabled";
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8192-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10700000 0 0x8000>,
+ <0 0x10720000 0 0xe0000>;
+ reg-names = "sram", "l1tcm", "cfg";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ status = "disabled";
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 06/17] arm64: dts: mt8192: Add xhci node
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
` (4 preceding siblings ...)
2022-02-17 13:40 ` [PATCH 05/17] arm64: dts: mt8192: Add SCP node Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 07/17] arm64: dts: mt8192: Add audio-related nodes Allen-KH Cheng
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add xhci node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9d9bb67bc65d..d56ac78620ee 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
@@ -717,6 +718,30 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt8192-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "host";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg CLK_INFRA_SSUSB>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>,
+ <&apmixedsys CLK_APMIXED_USBPLL>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 07/17] arm64: dts: mt8192: Add audio-related nodes
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
` (5 preceding siblings ...)
2022-02-17 13:40 ` [PATCH 06/17] arm64: dts: mt8192: Add xhci node Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 08/17] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 09/17] arm64: dts: mt8192: Correct nor_flash status of mt8192 Allen-KH Cheng
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
Move audsys node in ascending order.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
1 file changed, 128 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d56ac78620ee..92262a67ef68 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -742,6 +742,134 @@
#size-cells = <2>;
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
@@ -757,12 +885,6 @@
status = "disable";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
i2c3: i2c@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 08/17] arm64: dts: mt8192: Add PCIe node
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
` (6 preceding siblings ...)
2022-02-17 13:40 ` [PATCH 07/17] arm64: dts: mt8192: Add audio-related nodes Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
2022-02-17 13:40 ` [PATCH 09/17] arm64: dts: mt8192: Correct nor_flash status of mt8192 Allen-KH Cheng
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Add PCIe node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 92262a67ef68..723bfdc3a1aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -870,6 +870,44 @@
};
};
+ pcie: pcie@11230000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ reg = <0 0x11230000 0 0x2000>;
+ reg-names = "pcie-mac";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+ <&infracfg CLK_INFRA_PCIE_TL_96M>,
+ <&infracfg CLK_INFRA_PCIE_TL_32K>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+ <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+ <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+ "obff_ck0", "axi_ck0", "pipe_ck0";
+ assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+ resets = <&infracfg_rst 2>,
+ <&infracfg_rst 3>;
+ reset-names = "phy", "mac";
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+ <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 09/17] arm64: dts: mt8192: Correct nor_flash status of mt8192
2022-02-17 13:40 [PATCH 00/17] Add driver nodes for MT8192 SoC Allen-KH Cheng
` (7 preceding siblings ...)
2022-02-17 13:40 ` [PATCH 08/17] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
@ 2022-02-17 13:40 ` Allen-KH Cheng
8 siblings, 0 replies; 10+ messages in thread
From: Allen-KH Cheng @ 2022-02-17 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, --to=Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Allen-KH Cheng
Correct nor_flash status of mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 723bfdc3a1aa..87c0a30c9f73 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -920,7 +920,7 @@
assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disable";
+ status = "disabled";
};
i2c3: i2c@11cb0000 {
--
2.18.0
^ permalink raw reply [flat|nested] 10+ messages in thread