[PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests

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* [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests
@ 2022-03-29  7:29 Anup Patel
  2022-03-29  7:29 ` [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table Anup Patel
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Anup Patel @ 2022-03-29  7:29 UTC (permalink / raw)
  To: Paolo Bonzini, Atish Patra
  Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
	Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
	Anup Patel

Getting unexpected guest traps while running KVM RISC-V selftests should
cause the test to fail appropriately with VCPU register dump. This series
improves handling of unexpected traps along these lines.

These patches can also be found in riscv_kvm_selftests_unexp_trap_v1 branch
at: https://github.com/avpatel/linux.git

Anup Patel (3):
  KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
  KVM: selftests: riscv: Fix alignment of the guest_hang() function
  KVM: selftests: riscv: Improve unexpected guest trap handling

 .../selftests/kvm/include/riscv/processor.h   | 12 ++++---
 .../selftests/kvm/lib/riscv/processor.c       |  9 +++---
 tools/testing/selftests/kvm/lib/riscv/ucall.c | 31 +++++++++++++------
 3 files changed, 34 insertions(+), 18 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
  2022-03-29  7:29 [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Anup Patel
@ 2022-03-29  7:29 ` Anup Patel
  2022-04-05  7:18   ` Anup Patel
  2022-03-29  7:29 ` [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function Anup Patel
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 7+ messages in thread
From: Anup Patel @ 2022-03-29  7:29 UTC (permalink / raw)
  To: Paolo Bonzini, Atish Patra
  Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
	Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
	Anup Patel

Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always set
these bits in both G-stage (hypervisor) and VS-stage (guest kernel).

If PTE A and D bits are not set by software (hypervisor or guest)
then RISC-V implementations not supporting hardware updates of these
bits will cause traps even for perfectly valid PTEs.

Based on above explanation, the VS-stage page table created by various
KVM selftest applications is not correct because PTE A and D bits are
not set. This patch fixes VS-stage page table programming of PTE A and
D bits for KVM selftests.

Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 tools/testing/selftests/kvm/include/riscv/processor.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
index dc284c6bdbc3..eca5c622efd2 100644
--- a/tools/testing/selftests/kvm/include/riscv/processor.h
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -101,7 +101,9 @@ static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
 #define PGTBL_PTE_WRITE_SHIFT			2
 #define PGTBL_PTE_READ_MASK			0x0000000000000002ULL
 #define PGTBL_PTE_READ_SHIFT			1
-#define PGTBL_PTE_PERM_MASK			(PGTBL_PTE_EXECUTE_MASK | \
+#define PGTBL_PTE_PERM_MASK			(PGTBL_PTE_ACCESSED_MASK | \
+						 PGTBL_PTE_DIRTY_MASK | \
+						 PGTBL_PTE_EXECUTE_MASK | \
 						 PGTBL_PTE_WRITE_MASK | \
 						 PGTBL_PTE_READ_MASK)
 #define PGTBL_PTE_VALID_MASK			0x0000000000000001ULL
-- 
2.25.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
  2022-03-29  7:29 ` [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table Anup Patel
@ 2022-04-05  7:18   ` Anup Patel
  0 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2022-04-05  7:18 UTC (permalink / raw)
  To: Anup Patel
  Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
	Albert Ou, Alistair Francis, KVM General,
	open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv),
	linux-riscv, linux-kernel@vger.kernel.org List

On Tue, Mar 29, 2022 at 12:59 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Supporting hardware updates of PTE A and D bits is optional for any
> RISC-V implementation so current software strategy is to always set
> these bits in both G-stage (hypervisor) and VS-stage (guest kernel).
>
> If PTE A and D bits are not set by software (hypervisor or guest)
> then RISC-V implementations not supporting hardware updates of these
> bits will cause traps even for perfectly valid PTEs.
>
> Based on above explanation, the VS-stage page table created by various
> KVM selftest applications is not correct because PTE A and D bits are
> not set. This patch fixes VS-stage page table programming of PTE A and
> D bits for KVM selftests.
>
> Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
> 64-bit")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

I have queued this patch for RC fixes.

Thanks,
Anup

> ---
>  tools/testing/selftests/kvm/include/riscv/processor.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
> index dc284c6bdbc3..eca5c622efd2 100644
> --- a/tools/testing/selftests/kvm/include/riscv/processor.h
> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h
> @@ -101,7 +101,9 @@ static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
>  #define PGTBL_PTE_WRITE_SHIFT                  2
>  #define PGTBL_PTE_READ_MASK                    0x0000000000000002ULL
>  #define PGTBL_PTE_READ_SHIFT                   1
> -#define PGTBL_PTE_PERM_MASK                    (PGTBL_PTE_EXECUTE_MASK | \
> +#define PGTBL_PTE_PERM_MASK                    (PGTBL_PTE_ACCESSED_MASK | \
> +                                                PGTBL_PTE_DIRTY_MASK | \
> +                                                PGTBL_PTE_EXECUTE_MASK | \
>                                                  PGTBL_PTE_WRITE_MASK | \
>                                                  PGTBL_PTE_READ_MASK)
>  #define PGTBL_PTE_VALID_MASK                   0x0000000000000001ULL
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function
  2022-03-29  7:29 [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Anup Patel
  2022-03-29  7:29 ` [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table Anup Patel
@ 2022-03-29  7:29 ` Anup Patel
  2022-04-05  7:18   ` Anup Patel
  2022-03-29  7:29 ` [PATCH 3/3] KVM: selftests: riscv: Improve unexpected guest trap handling Anup Patel
  2022-04-04  4:11 ` [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Mayuresh Chitale
  3 siblings, 1 reply; 7+ messages in thread
From: Anup Patel @ 2022-03-29  7:29 UTC (permalink / raw)
  To: Paolo Bonzini, Atish Patra
  Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
	Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
	Anup Patel

The guest_hang() function is used as the default exception handler
for various KVM selftests applications by setting it's address in
the vstvec CSR. The vstvec CSR requires exception handler base address
to be at least 4-byte aligned so this patch fixes alignment of the
guest_hang() function.

Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 tools/testing/selftests/kvm/lib/riscv/processor.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index d377f2603d98..3961487a4870 100644
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -268,7 +268,7 @@ void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
 		core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
 }
 
-static void guest_hang(void)
+static void __aligned(16) guest_hang(void)
 {
 	while (1)
 		;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function
  2022-03-29  7:29 ` [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function Anup Patel
@ 2022-04-05  7:18   ` Anup Patel
  0 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2022-04-05  7:18 UTC (permalink / raw)
  To: Anup Patel
  Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
	Albert Ou, Alistair Francis, KVM General,
	open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv),
	linux-riscv, linux-kernel@vger.kernel.org List

On Tue, Mar 29, 2022 at 12:59 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The guest_hang() function is used as the default exception handler
> for various KVM selftests applications by setting it's address in
> the vstvec CSR. The vstvec CSR requires exception handler base address
> to be at least 4-byte aligned so this patch fixes alignment of the
> guest_hang() function.
>
> Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
> 64-bit")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

I have queued this patch for RC fixes.

Thanks,
Anup

> ---
>  tools/testing/selftests/kvm/lib/riscv/processor.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
> index d377f2603d98..3961487a4870 100644
> --- a/tools/testing/selftests/kvm/lib/riscv/processor.c
> +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
> @@ -268,7 +268,7 @@ void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
>                 core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
>  }
>
> -static void guest_hang(void)
> +static void __aligned(16) guest_hang(void)
>  {
>         while (1)
>                 ;
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 3/3] KVM: selftests: riscv: Improve unexpected guest trap handling
  2022-03-29  7:29 [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Anup Patel
  2022-03-29  7:29 ` [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table Anup Patel
  2022-03-29  7:29 ` [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function Anup Patel
@ 2022-03-29  7:29 ` Anup Patel
  2022-04-04  4:11 ` [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Mayuresh Chitale
  3 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2022-03-29  7:29 UTC (permalink / raw)
  To: Paolo Bonzini, Atish Patra
  Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
	Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
	Anup Patel

Currently, we simply hang using "while (1) ;" upon any unexpected
guest traps because the default guest trap handler is guest_hang().

The above approach is not useful to anyone because KVM selftests
users will only see a hung application upon any unexpected guest
trap.

This patch improves unexpected guest trap handling for KVM RISC-V
selftests by doing the following:
1) Return to host user-space
2) Dump VCPU registers
3) Die using TEST_ASSERT(0, ...)

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 .../selftests/kvm/include/riscv/processor.h   |  8 +++--
 .../selftests/kvm/lib/riscv/processor.c       |  9 +++---
 tools/testing/selftests/kvm/lib/riscv/ucall.c | 31 +++++++++++++------
 3 files changed, 31 insertions(+), 17 deletions(-)

diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
index eca5c622efd2..4fcfd1c0389d 100644
--- a/tools/testing/selftests/kvm/include/riscv/processor.h
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -119,10 +119,12 @@ static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
 #define SATP_ASID_SHIFT				44
 #define SATP_ASID_MASK				_AC(0xFFFF, UL)
 
-#define SBI_EXT_EXPERIMENTAL_START	0x08000000
-#define SBI_EXT_EXPERIMENTAL_END	0x08FFFFFF
+#define SBI_EXT_EXPERIMENTAL_START		0x08000000
+#define SBI_EXT_EXPERIMENTAL_END		0x08FFFFFF
 
-#define KVM_RISCV_SELFTESTS_SBI_EXT	SBI_EXT_EXPERIMENTAL_END
+#define KVM_RISCV_SELFTESTS_SBI_EXT		SBI_EXT_EXPERIMENTAL_END
+#define KVM_RISCV_SELFTESTS_SBI_UCALL		0
+#define KVM_RISCV_SELFTESTS_SBI_UNEXP		1
 
 struct sbiret {
 	long error;
diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index 3961487a4870..56e4705f7744 100644
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -268,10 +268,11 @@ void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
 		core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
 }
 
-static void __aligned(16) guest_hang(void)
+static void __aligned(16) guest_unexp_trap(void)
 {
-	while (1)
-		;
+	sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT,
+		  KVM_RISCV_SELFTESTS_SBI_UNEXP,
+		  0, 0, 0, 0, 0, 0);
 }
 
 void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code)
@@ -310,7 +311,7 @@ void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code)
 
 	/* Setup default exception vector of guest */
 	set_reg(vm, vcpuid, RISCV_CSR_REG(stvec),
-		(unsigned long)guest_hang);
+		(unsigned long)guest_unexp_trap);
 }
 
 void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...)
diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
index 9e42d8248fa6..8550f424d093 100644
--- a/tools/testing/selftests/kvm/lib/riscv/ucall.c
+++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
@@ -60,8 +60,9 @@ void ucall(uint64_t cmd, int nargs, ...)
 		uc.args[i] = va_arg(va, uint64_t);
 	va_end(va);
 
-	sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 0, (vm_vaddr_t)&uc,
-		  0, 0, 0, 0, 0);
+	sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT,
+		  KVM_RISCV_SELFTESTS_SBI_UCALL,
+		  (vm_vaddr_t)&uc, 0, 0, 0, 0, 0);
 }
 
 uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
@@ -73,14 +74,24 @@ uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
 		memset(uc, 0, sizeof(*uc));
 
 	if (run->exit_reason == KVM_EXIT_RISCV_SBI &&
-	    run->riscv_sbi.extension_id == KVM_RISCV_SELFTESTS_SBI_EXT &&
-	    run->riscv_sbi.function_id == 0) {
-		memcpy(&ucall, addr_gva2hva(vm, run->riscv_sbi.args[0]),
-			sizeof(ucall));
-
-		vcpu_run_complete_io(vm, vcpu_id);
-		if (uc)
-			memcpy(uc, &ucall, sizeof(ucall));
+	    run->riscv_sbi.extension_id == KVM_RISCV_SELFTESTS_SBI_EXT) {
+		switch (run->riscv_sbi.function_id) {
+		case KVM_RISCV_SELFTESTS_SBI_UCALL:
+			memcpy(&ucall, addr_gva2hva(vm,
+			       run->riscv_sbi.args[0]), sizeof(ucall));
+
+			vcpu_run_complete_io(vm, vcpu_id);
+			if (uc)
+				memcpy(uc, &ucall, sizeof(ucall));
+
+			break;
+		case KVM_RISCV_SELFTESTS_SBI_UNEXP:
+			vcpu_dump(stderr, vm, vcpu_id, 2);
+			TEST_ASSERT(0, "Unexpected trap taken by guest");
+			break;
+		default:
+			break;
+		}
 	}
 
 	return ucall.cmd;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests
  2022-03-29  7:29 [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Anup Patel
                   ` (2 preceding siblings ...)
  2022-03-29  7:29 ` [PATCH 3/3] KVM: selftests: riscv: Improve unexpected guest trap handling Anup Patel
@ 2022-04-04  4:11 ` Mayuresh Chitale
  3 siblings, 0 replies; 7+ messages in thread
From: Mayuresh Chitale @ 2022-04-04  4:11 UTC (permalink / raw)
  To: Anup Patel
  Cc: Paolo Bonzini, Atish Patra, Palmer Dabbelt, Paul Walmsley,
	Albert Ou, Alistair Francis, Anup Patel, kvm, kvm-riscv,
	linux-riscv, linux-kernel

On Tue, Mar 29, 2022 at 1:00 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Getting unexpected guest traps while running KVM RISC-V selftests should
> cause the test to fail appropriately with VCPU register dump. This series
> improves handling of unexpected traps along these lines.
>
> These patches can also be found in riscv_kvm_selftests_unexp_trap_v1 branch
> at: https://github.com/avpatel/linux.git
>
> Anup Patel (3):
>   KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
>   KVM: selftests: riscv: Fix alignment of the guest_hang() function
>   KVM: selftests: riscv: Improve unexpected guest trap handling
>
>  .../selftests/kvm/include/riscv/processor.h   | 12 ++++---
>  .../selftests/kvm/lib/riscv/processor.c       |  9 +++---
>  tools/testing/selftests/kvm/lib/riscv/ucall.c | 31 +++++++++++++------
>  3 files changed, 34 insertions(+), 18 deletions(-)
>
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

I have tested the series on Qemu.

Tested-by: Mayuresh Chitale <mchitale@ventanamicro.com>

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2022-04-05  7:21 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
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2022-04-05  7:18   ` Anup Patel
2022-03-29  7:29 ` [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function Anup Patel
2022-04-05  7:18   ` Anup Patel
2022-03-29  7:29 ` [PATCH 3/3] KVM: selftests: riscv: Improve unexpected guest trap handling Anup Patel
2022-04-04  4:11 ` [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Mayuresh Chitale

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