From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>
Cc: <pbonzini@redhat.com>, <mlevitsk@redhat.com>, <seanjc@google.com>,
<joro@8bytes.org>, <jon.grimm@amd.com>, <wei.huang2@amd.com>,
<terry.bowman@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v3 11/14] KVM: SVM: Introduce hybrid-AVIC mode
Date: Wed, 4 May 2022 02:31:25 -0500 [thread overview]
Message-ID: <20220504073128.12031-12-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20220504073128.12031-1-suravee.suthikulpanit@amd.com>
Currently, AVIC is inhibited when booting a VM w/ x2APIC support.
because AVIC cannot virtualize x2APIC MSR register accesses.
However, the AVIC doorbell can be used to accelerate interrupt
injection into a running vCPU, while all guest accesses to x2APIC MSRs
will be intercepted and emulated by KVM.
With hybrid-AVIC support, the APICV_INHIBIT_REASON_X2APIC is
no longer enforced.
Suggested-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
arch/x86/kvm/svm/avic.c | 10 +++++++++-
arch/x86/kvm/svm/svm.c | 9 ---------
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index d07c58f06bed..3b6a96043633 100644
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -92,12 +92,20 @@ static void avic_activate_vmcb(struct vcpu_svm *svm)
vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK;
vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
- if (apic_x2apic_mode(svm->vcpu.arch.apic)) {
+
+ /* Note:
+ * KVM can support hybrid-x2AVIC mode, where KVM emulates x2APIC
+ * MSR accesses, while interrupt injection to a running vCPU
+ * can be achieve using AVIC doorbell.
+ */
+ if (apic_x2apic_mode(svm->vcpu.arch.apic) &&
+ (avic_mode == AVIC_MODE_X2)) {
vmcb->control.int_ctl |= X2APIC_MODE_MASK;
vmcb->control.avic_physical_id |= X2AVIC_MAX_PHYSICAL_ID;
/* Disabling MSR intercept for x2APIC registers */
avic_set_x2apic_msr_interception(svm, false);
} else {
+ /* For xAVIC and hybrid-x2AVIC modes */
vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID;
/* Enabling MSR intercept for x2APIC registers */
avic_set_x2apic_msr_interception(svm, true);
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 96a1fc1a1d1b..c0a3d4a1f3dc 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -4041,7 +4041,6 @@ static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
struct kvm_cpuid_entry2 *best;
- struct kvm *kvm = vcpu->kvm;
vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
boot_cpu_has(X86_FEATURE_XSAVE) &&
@@ -4073,14 +4072,6 @@ static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
}
- if (kvm_vcpu_apicv_active(vcpu)) {
- /*
- * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
- * is exposed to the guest, disable AVIC.
- */
- if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
- kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_X2APIC);
- }
init_vmcb_after_set_cpuid(vcpu);
}
--
2.25.1
next prev parent reply other threads:[~2022-05-04 7:33 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 7:31 [PATCH v3 00/14] Introducing AMD x2AVIC and hybrid-AVIC modes Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 01/14] x86/cpufeatures: Introduce x2AVIC CPUID bit Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 02/14] KVM: x86: lapic: Rename [GET/SET]_APIC_DEST_FIELD to [GET/SET]_XAPIC_DEST_FIELD Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 03/14] KVM: SVM: Detect X2APIC virtualization (x2AVIC) support Suravee Suthikulpanit
2022-05-04 12:12 ` Maxim Levitsky
2022-05-05 4:07 ` Suravee Suthikulpanit
2022-05-05 7:38 ` Maxim Levitsky
2022-05-04 7:31 ` [PATCH v3 04/14] KVM: SVM: Update max number of vCPUs supported for x2AVIC mode Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 05/14] KVM: SVM: Update avic_kick_target_vcpus to support 32-bit APIC ID Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 06/14] KVM: SVM: Do not support updating APIC ID when in x2APIC mode Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 07/14] KVM: SVM: Adding support for configuring x2APIC MSRs interception Suravee Suthikulpanit
2022-05-04 12:14 ` Maxim Levitsky
2022-05-04 7:31 ` [PATCH v3 08/14] KVM: SVM: Update AVIC settings when changing APIC mode Suravee Suthikulpanit
2022-05-04 12:19 ` Maxim Levitsky
2022-05-05 1:38 ` Suravee Suthikulpanit
2022-05-05 7:34 ` Maxim Levitsky
2022-05-04 7:31 ` [PATCH v3 09/14] KVM: SVM: Introduce helper functions to (de)activate AVIC and x2AVIC Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 10/14] KVM: SVM: Do not throw warning when calling avic_vcpu_load on a running vcpu Suravee Suthikulpanit
2022-05-04 7:31 ` Suravee Suthikulpanit [this message]
2022-05-04 12:32 ` [PATCH v3 11/14] KVM: SVM: Introduce hybrid-AVIC mode Maxim Levitsky
2022-05-05 3:57 ` Suravee Suthikulpanit
2022-05-04 7:31 ` [PATCH v3 12/14] kvm/x86: Warning APICv inconsistency only when vcpu APIC mode is valid Suravee Suthikulpanit
2022-05-04 12:33 ` Maxim Levitsky
2022-05-04 7:31 ` [PATCH v3 13/14] KVM: SVM: Use target APIC ID to complete x2AVIC IRQs when possible Suravee Suthikulpanit
2022-05-04 12:34 ` Maxim Levitsky
2022-05-04 7:31 ` [PATCH v3 14/14] KVM: SVM: Add AVIC doorbell tracepoint Suravee Suthikulpanit
2022-05-04 12:36 ` Maxim Levitsky
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