From: Ashok Raj <ashok.raj@intel.com>
To: Borislav Petkov <bp@alien8.de>, Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
"LKML Mailing List" <linux-kernel@vger.kernel.org>,
X86-kernel <x86@kernel.org>,
Andy Lutomirski <luto@amacapital.net>,
Tom Lendacky <thomas.lendacky@amd.com>,
"Jacon Jun Pan" <jacob.jun.pan@intel.com>,
Ashok Raj <ashok.raj@intel.com>
Subject: [PATCH v3 0/5] Making microcode late-load robust
Date: Wed, 17 Aug 2022 05:11:22 +0000 [thread overview]
Message-ID: <20220817051127.3323755-1-ashok.raj@intel.com> (raw)
Hi Boris
I thought v2 worked, but there were some glaring errors in them.
I added more trace and this did go through and finish. More testing would
help.
Let me know how you want to handle 1-3. patch4,5 needs more review and some
help testing on AMD as well.
v2: https://lore.kernel.org/lkml/20220816043754.3258815-1-ashok.raj@intel.com/
v1: https://lore.kernel.org/lkml/20220813223825.3164861-1-ashok.raj@intel.com/
Changes since v2
- Dropped Documentation, queued for tip
https://lore.kernel.org/lkml/166063601497.401.9527776956724011207.tip-bot2@tip-bot2/
Patches: 1-3
No Changes since v1
Patch4:
x2apic doesn't handle NMI vector via the self IPI MSR, it can only
send Fixed mode interrupts. Enhance send_IPI_self() to comprehend
and use a function that will deliver to the NMI.
Patch5:
- Modified when the NMI was triggered. Moved it closer to when
__reload_late() is running.
- Used the new apic->send_IPI_self() support helper.
- Added an atomic to check if the primary has completed the load.
- Triggering the NMI and when its taken determines how long the primary
CPU needs to wait. For Now i have no timeout, but will check on couple
more platforms before coming with a number, so it can bail out if
secondaries don't show up in a reasonable amount of time.
Ashok Raj (5):
x86/microcode/intel: Check against CPU signature before saving
microcode
x86/microcode/intel: Allow a late-load only if a min rev is specified
x86/microcode: Avoid any chance of MCE's during microcode update
x86/x2apic: Support x2apic self IPI with NMI_VECTOR
x86/microcode: Place siblings in NMI loop while update in progress
arch/x86/include/asm/mce.h | 4 +
arch/x86/include/asm/microcode_intel.h | 4 +-
arch/x86/kernel/apic/x2apic_phys.c | 6 +-
arch/x86/kernel/cpu/mce/core.c | 9 +
arch/x86/kernel/cpu/microcode/core.c | 229 ++++++++++++++++++++++++-
arch/x86/kernel/cpu/microcode/intel.c | 34 +++-
6 files changed, 274 insertions(+), 12 deletions(-)
--
2.32.0
next reply other threads:[~2022-08-17 5:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-17 5:11 Ashok Raj [this message]
2022-08-17 5:11 ` [PATCH v3 1/5] x86/microcode/intel: Check against CPU signature before saving microcode Ashok Raj
2022-08-17 7:43 ` Ingo Molnar
2022-08-17 10:45 ` Ashok Raj
2022-08-19 10:24 ` Borislav Petkov
2022-08-23 11:13 ` Ashok Raj
2022-08-24 19:27 ` Borislav Petkov
2022-08-25 3:27 ` Ashok Raj
2022-08-26 16:24 ` Borislav Petkov
2022-08-26 17:18 ` Ashok Raj
2022-08-26 17:29 ` Borislav Petkov
2022-08-17 5:11 ` [PATCH v3 2/5] x86/microcode/intel: Allow a late-load only if a min rev is specified Ashok Raj
2022-08-17 7:45 ` Ingo Molnar
2022-08-19 11:11 ` Borislav Petkov
2022-08-23 0:08 ` Ashok Raj
2022-08-24 19:52 ` Borislav Petkov
2022-08-25 4:02 ` Ashok Raj
2022-08-26 12:09 ` Borislav Petkov
2022-08-17 5:11 ` [PATCH v3 3/5] x86/microcode: Avoid any chance of MCE's during microcode update Ashok Raj
2022-08-17 7:41 ` Ingo Molnar
2022-08-17 7:58 ` Ingo Molnar
2022-08-17 8:09 ` Borislav Petkov
2022-08-17 11:57 ` Ashok Raj
2022-08-17 12:10 ` Borislav Petkov
2022-08-17 12:30 ` Ashok Raj
2022-08-17 14:19 ` Borislav Petkov
2022-08-17 15:06 ` Ashok Raj
2022-08-29 14:23 ` Andy Lutomirski
2022-08-17 11:40 ` Ashok Raj
2022-08-17 5:11 ` [PATCH v3 4/5] x86/x2apic: Support x2apic self IPI with NMI_VECTOR Ashok Raj
2022-08-17 5:11 ` [PATCH v3 5/5] x86/microcode: Place siblings in NMI loop while update in progress Ashok Raj
2022-08-30 19:15 ` Andy Lutomirski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220817051127.3323755-1-ashok.raj@intel.com \
--to=ashok.raj@intel.com \
--cc=bp@alien8.de \
--cc=dave.hansen@intel.com \
--cc=jacob.jun.pan@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=luto@amacapital.net \
--cc=tglx@linutronix.de \
--cc=thomas.lendacky@amd.com \
--cc=tony.luck@intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®