From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, seanjc@google.com, kvm@vger.kernel.org
Cc: like.xu.linux@gmail.com, kan.liang@linux.intel.com,
wei.w.wang@intel.com, linux-kernel@vger.kernel.org
Subject: [PATCH 08/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list
Date: Wed, 31 Aug 2022 18:34:31 -0400 [thread overview]
Message-ID: <20220831223438.413090-9-weijiang.yang@intel.com> (raw)
In-Reply-To: <20220831223438.413090-1-weijiang.yang@intel.com>
Arch LBR MSR_ARCH_LBR_DEPTH and MSR_ARCH_LBR_CTL are queried by
userspace application before it wants to {save|restore} the Arch LBR
data. Other LBR related data MSRs are omitted here intentionally due
to lengthy list(32*3). Userspace can still use KVM_{GET|SET}_MSRS to
access them if necessary.
Suggested-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
---
arch/x86/kvm/x86.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 92ff5f7d944b..b3d2a7ad1d18 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1452,6 +1452,7 @@ static const u32 msrs_to_save_all[] = {
MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
MSR_IA32_XFD, MSR_IA32_XFD_ERR,
MSR_IA32_XSS,
+ MSR_ARCH_LBR_CTL, MSR_ARCH_LBR_DEPTH,
};
static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
@@ -3839,6 +3840,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_PEBS_ENABLE:
case MSR_IA32_DS_AREA:
case MSR_PEBS_DATA_CFG:
+ case MSR_ARCH_LBR_CTL:
+ case MSR_ARCH_LBR_DEPTH:
case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
if (kvm_pmu_is_valid_msr(vcpu, msr))
return kvm_pmu_set_msr(vcpu, msr_info);
@@ -3942,6 +3945,8 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_PEBS_ENABLE:
case MSR_IA32_DS_AREA:
case MSR_PEBS_DATA_CFG:
+ case MSR_ARCH_LBR_CTL:
+ case MSR_ARCH_LBR_DEPTH:
case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
return kvm_pmu_get_msr(vcpu, msr_info);
@@ -6948,6 +6953,11 @@ static void kvm_init_msr_list(void)
if (!kvm_caps.supported_xss)
continue;
break;
+ case MSR_ARCH_LBR_DEPTH:
+ case MSR_ARCH_LBR_CTL:
+ if (!kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR))
+ continue;
+ break;
default:
break;
}
--
2.27.0
next prev parent reply other threads:[~2022-09-01 1:37 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 22:34 [PATCH 00/15] Introduce Architectural LBR for vPMU Yang Weijiang
2022-08-31 22:34 ` [PATCH 01/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2022-09-01 14:19 ` Sean Christopherson
2022-09-02 3:05 ` Yang, Weijiang
2022-08-31 22:34 ` [PATCH 02/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2022-08-31 22:34 ` [PATCH 03/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2022-08-31 22:34 ` [PATCH 04/15] KVM: PMU: disable LBR handling if architectural LBR is available Yang Weijiang
2022-08-31 22:34 ` [PATCH 05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2022-08-31 22:34 ` [PATCH 06/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2022-08-31 22:34 ` [PATCH 07/15] KVM: VMX: Support passthrough of architectural LBRs Yang Weijiang
2022-09-01 14:20 ` Sean Christopherson
2022-09-02 3:04 ` Yang, Weijiang
2022-08-31 22:34 ` Yang Weijiang [this message]
2022-08-31 22:34 ` [PATCH 09/15] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2022-08-31 22:34 ` [PATCH 10/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2022-08-31 22:34 ` [PATCH 11/15] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2022-08-31 22:34 ` [PATCH 12/15] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2022-08-31 22:34 ` [PATCH 13/15] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Yang Weijiang
2022-08-31 22:34 ` [PATCH 14/15] KVM: x86: Add Arch LBR data MSR access interface Yang Weijiang
2022-08-31 22:34 ` [PATCH 15/15] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID Yang Weijiang
2022-09-01 14:23 ` [PATCH 00/15] Introduce Architectural LBR for vPMU Sean Christopherson
2022-09-02 3:44 ` Yang, Weijiang
2022-10-21 2:14 ` Yang, Weijiang
2022-10-30 6:06 ` Yang, Weijiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220831223438.413090-9-weijiang.yang@intel.com \
--to=weijiang.yang@intel.com \
--cc=kan.liang@linux.intel.com \
--cc=kvm@vger.kernel.org \
--cc=like.xu.linux@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
--cc=wei.w.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®