From: "Yang, Weijiang" <weijiang.yang@intel.com>
To: Sean Christopherson <seanjc@google.com>
Cc: "pbonzini@redhat.com" <pbonzini@redhat.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"like.xu.linux@gmail.com" <like.xu.linux@gmail.com>,
"kan.liang@linux.intel.com" <kan.liang@linux.intel.com>,
"Wang, Wei W" <wei.w.wang@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 00/15] Introduce Architectural LBR for vPMU
Date: Fri, 2 Sep 2022 11:44:22 +0800 [thread overview]
Message-ID: <8b484c6e-915c-a7f6-d2a7-cf80ff67b63e@intel.com> (raw)
In-Reply-To: <YxDAa6sV1CUyGpoN@google.com>
On 9/1/2022 10:23 PM, Sean Christopherson wrote:
> On Wed, Aug 31, 2022, Yang Weijiang wrote:
>> The old patch series was queued in KVM/queue for a while and finally
>> moved to below branch after Paolo's refactor. This new patch set is
>> built on top of Paolo's work + some fixes, it's tested on legacy platform
> Please elaborate on what was broken, i.e. why this was de-queued, as well as on
> what was fixed an dhow. That will help bring me up to speed and expedite review.
Thanks Sean!
The de-queued reason I read from community is, the PEBS and Arch-LBR
patches broke
selftest/KUTs due to host-initiated 0 writes to PMU msrs. Paolo tried to
fix it but you
didn't agree on the solution. Plus your comments below:
On 6/1/2022 4:54 PM, Paolo Bonzini wrote:
> On 5/31/22 20:37, Sean Christopherson wrote:
>> Can we just punt this out of kvm/queue until its been properly reviewed?
> Yes, I agree. I have started making some changes and pushed the
> result to kvm/arch-lbr-for-weijiang.
What are fixed in this series:
1. An missing of -1: if ((entry->eax & 0xff) != (1 << (depth_bit - 1)))
2. Removed exit bit check in cpu_has_vmx_arch_lbr(void), moved it to
setup_vmcs_config().
3. A redundant check kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) in
kvm_check_cpuid().
4. KUT/selftest failures due to lack of MSR_ARCH_LBR_CTL and
MSR_ARCH_LBR_DEPTH in kvm_set_msr_common() before validate pmu msrs.
5. Calltrace in L1 when L1 tried to vmcs_write64(GUEST_IA32_LBR_CTL, 0)
in vmx_vcpu_reset(), use cpu_has_vmx_arch_lbr() instead.
6. Removed VM_ENTRY_LOAD_IA32_LBR_CTL and VM_EXIT_CLEAR_IA32_LBR_CTL
from exec_control in nested case.
next prev parent reply other threads:[~2022-09-02 3:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 22:34 Yang Weijiang
2022-08-31 22:34 ` [PATCH 01/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2022-09-01 14:19 ` Sean Christopherson
2022-09-02 3:05 ` Yang, Weijiang
2022-08-31 22:34 ` [PATCH 02/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2022-08-31 22:34 ` [PATCH 03/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2022-08-31 22:34 ` [PATCH 04/15] KVM: PMU: disable LBR handling if architectural LBR is available Yang Weijiang
2022-08-31 22:34 ` [PATCH 05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2022-08-31 22:34 ` [PATCH 06/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2022-08-31 22:34 ` [PATCH 07/15] KVM: VMX: Support passthrough of architectural LBRs Yang Weijiang
2022-09-01 14:20 ` Sean Christopherson
2022-09-02 3:04 ` Yang, Weijiang
2022-08-31 22:34 ` [PATCH 08/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2022-08-31 22:34 ` [PATCH 09/15] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2022-08-31 22:34 ` [PATCH 10/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2022-08-31 22:34 ` [PATCH 11/15] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2022-08-31 22:34 ` [PATCH 12/15] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2022-08-31 22:34 ` [PATCH 13/15] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Yang Weijiang
2022-08-31 22:34 ` [PATCH 14/15] KVM: x86: Add Arch LBR data MSR access interface Yang Weijiang
2022-08-31 22:34 ` [PATCH 15/15] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID Yang Weijiang
2022-09-01 14:23 ` [PATCH 00/15] Introduce Architectural LBR for vPMU Sean Christopherson
2022-09-02 3:44 ` Yang, Weijiang [this message]
2022-10-21 2:14 ` Yang, Weijiang
2022-10-30 6:06 ` Yang, Weijiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8b484c6e-915c-a7f6-d2a7-cf80ff67b63e@intel.com \
--to=weijiang.yang@intel.com \
--cc=kan.liang@linux.intel.com \
--cc=kvm@vger.kernel.org \
--cc=like.xu.linux@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
--cc=wei.w.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®