* [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema
2022-11-24 8:41 [PATCH v5 0/4] x86/of: Add support for interrupt mode config for x86 OF systems Rahul Tanwar
@ 2022-11-24 8:41 ` Rahul Tanwar
2022-11-30 21:21 ` Rob Herring
2022-12-02 14:04 ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Rahul Tanwar
` (2 subsequent siblings)
3 siblings, 2 replies; 11+ messages in thread
From: Rahul Tanwar @ 2022-11-24 8:41 UTC (permalink / raw)
To: Rahul Tanwar, Andy Shevchenko, linux-kernel, devicetree
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
linux-lgm-soc
Intel's APIC family of interrupt controllers support local APIC
(lapic) & I/O APIC (ioapic). Convert existing bindings for lapic
& ioapic from text to YAML schema. Separate lapic & ioapic schemas.
Addditionally, add description which was missing in text file and
add few more required standard properties which were also missing
in text file.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
.../intel,ce4100-ioapic.txt | 26 --------
.../intel,ce4100-ioapic.yaml | 60 +++++++++++++++++++
.../intel,ce4100-lapic.yaml | 57 ++++++++++++++++++
3 files changed, 117 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
deleted file mode 100644
index 7d19f494f19a..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Interrupt chips
----------------
-
-* Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
-
- Required properties:
- --------------------
- compatible = "intel,ce4100-ioapic";
- #interrupt-cells = <2>;
-
- Device's interrupt property:
-
- interrupts = <P S>;
-
- The first number (P) represents the interrupt pin which is wired to the
- IO APIC. The second number (S) represents the sense of interrupt which
- should be configured and can be one of:
- 0 - Edge Rising
- 1 - Level Low
- 2 - Level High
- 3 - Edge Falling
-
-* Local APIC
- Required property:
-
- compatible = "intel,ce4100-lapic";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
new file mode 100644
index 000000000000..39ab8cdd19b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+description: |
+ Intel's Advanced Programmable Interrupt Controller (APIC) is a
+ family of interrupt controllers. The APIC is a split
+ architecture design, with a local component (LAPIC) integrated
+ into the processor itself and an external I/O APIC. Local APIC
+ (lapic) receives interrupts from the processor's interrupt pins,
+ from internal sources and from an external I/O APIC (ioapic).
+ And it sends these to the processor core for handling.
+ See [1] Chapter 8 for more details.
+
+ Many of the Intel's generic devices like hpet, ioapic, lapic have
+ the ce4100 name in their compatible property names because they
+ first appeared in CE4100 SoC.
+
+ This schema defines bindings for I/O APIC interrupt controller.
+
+ [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
+
+properties:
+ compatible:
+ const: intel,ce4100-ioapic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ ioapic1: interrupt-controller@fec00000 {
+ compatible = "intel,ce4100-ioapic";
+ reg = <0xfec00000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
new file mode 100644
index 000000000000..55184cb49432
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+description: |
+ Intel's Advanced Programmable Interrupt Controller (APIC) is a
+ family of interrupt controllers. The APIC is a split
+ architecture design, with a local component (LAPIC) integrated
+ into the processor itself and an external I/O APIC. Local APIC
+ (lapic) receives interrupts from the processor's interrupt pins,
+ from internal sources and from an external I/O APIC (ioapic).
+ And it sends these to the processor core for handling.
+ See [1] Chapter 8 for more details.
+
+ Many of the Intel's generic devices like hpet, ioapic, lapic have
+ the ce4100 name in their compatible property names because they
+ first appeared in CE4100 SoC.
+
+ This schema defines bindings for local APIC interrupt controller.
+
+ [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
+
+properties:
+ compatible:
+ const: intel,ce4100-lapic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ lapic0: interrupt-controller@fee00000 {
+ compatible = "intel,ce4100-lapic";
+ reg = <0xfee00000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema
2022-11-24 8:41 ` [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Rahul Tanwar
@ 2022-11-30 21:21 ` Rob Herring
2022-12-02 14:04 ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
1 sibling, 0 replies; 11+ messages in thread
From: Rob Herring @ 2022-11-30 21:21 UTC (permalink / raw)
To: Rahul Tanwar
Cc: devicetree, Andy Shevchenko, H. Peter Anvin, Rob Herring,
Krzysztof Kozlowski, Marc Zyngier, linux-kernel, Ingo Molnar,
Dave Hansen, linux-lgm-soc, x86, Borislav Petkov,
Thomas Gleixner
On Thu, 24 Nov 2022 16:41:40 +0800, Rahul Tanwar wrote:
> Intel's APIC family of interrupt controllers support local APIC
> (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic
> & ioapic from text to YAML schema. Separate lapic & ioapic schemas.
> Addditionally, add description which was missing in text file and
> add few more required standard properties which were also missing
> in text file.
>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
> ---
> .../intel,ce4100-ioapic.txt | 26 --------
> .../intel,ce4100-ioapic.yaml | 60 +++++++++++++++++++
> .../intel,ce4100-lapic.yaml | 57 ++++++++++++++++++
> 3 files changed, 117 insertions(+), 26 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [tip: x86/apic] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema
2022-11-24 8:41 ` [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Rahul Tanwar
2022-11-30 21:21 ` Rob Herring
@ 2022-12-02 14:04 ` tip-bot2 for Rahul Tanwar
1 sibling, 0 replies; 11+ messages in thread
From: tip-bot2 for Rahul Tanwar @ 2022-12-02 14:04 UTC (permalink / raw)
To: linux-tip-commits
Cc: Andy Shevchenko, Rahul Tanwar, Thomas Gleixner, Rob Herring, x86,
linux-kernel
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 2b822f474621bb2f4f21dd6dae6900e2ccca7e95
Gitweb: https://git.kernel.org/tip/2b822f474621bb2f4f21dd6dae6900e2ccca7e95
Author: Rahul Tanwar <rtanwar@maxlinear.com>
AuthorDate: Thu, 24 Nov 2022 16:41:40 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 02 Dec 2022 14:57:13 +01:00
dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema
The DT bindings for X86 local APIC (lapic) and I/O APIC (ioapic) are
outdated. Rework them:
- Convert the bindings for lapic and ioapic from text to YAML schema.
- Separate lapic & ioapic schemas.
- Add missing but required standard properties
- Add missing descriptions
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221124084143.21841-2-rtanwar@maxlinear.com
---
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt | 26 --------------------------
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 117 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
deleted file mode 100644
index 7d19f49..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Interrupt chips
----------------
-
-* Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
-
- Required properties:
- --------------------
- compatible = "intel,ce4100-ioapic";
- #interrupt-cells = <2>;
-
- Device's interrupt property:
-
- interrupts = <P S>;
-
- The first number (P) represents the interrupt pin which is wired to the
- IO APIC. The second number (S) represents the sense of interrupt which
- should be configured and can be one of:
- 0 - Edge Rising
- 1 - Level Low
- 2 - Level High
- 3 - Edge Falling
-
-* Local APIC
- Required property:
-
- compatible = "intel,ce4100-lapic";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
new file mode 100644
index 0000000..39ab8cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+description: |
+ Intel's Advanced Programmable Interrupt Controller (APIC) is a
+ family of interrupt controllers. The APIC is a split
+ architecture design, with a local component (LAPIC) integrated
+ into the processor itself and an external I/O APIC. Local APIC
+ (lapic) receives interrupts from the processor's interrupt pins,
+ from internal sources and from an external I/O APIC (ioapic).
+ And it sends these to the processor core for handling.
+ See [1] Chapter 8 for more details.
+
+ Many of the Intel's generic devices like hpet, ioapic, lapic have
+ the ce4100 name in their compatible property names because they
+ first appeared in CE4100 SoC.
+
+ This schema defines bindings for I/O APIC interrupt controller.
+
+ [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
+
+properties:
+ compatible:
+ const: intel,ce4100-ioapic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ ioapic1: interrupt-controller@fec00000 {
+ compatible = "intel,ce4100-ioapic";
+ reg = <0xfec00000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
new file mode 100644
index 0000000..55184cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+description: |
+ Intel's Advanced Programmable Interrupt Controller (APIC) is a
+ family of interrupt controllers. The APIC is a split
+ architecture design, with a local component (LAPIC) integrated
+ into the processor itself and an external I/O APIC. Local APIC
+ (lapic) receives interrupts from the processor's interrupt pins,
+ from internal sources and from an external I/O APIC (ioapic).
+ And it sends these to the processor core for handling.
+ See [1] Chapter 8 for more details.
+
+ Many of the Intel's generic devices like hpet, ioapic, lapic have
+ the ce4100 name in their compatible property names because they
+ first appeared in CE4100 SoC.
+
+ This schema defines bindings for local APIC interrupt controller.
+
+ [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
+
+properties:
+ compatible:
+ const: intel,ce4100-lapic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ lapic0: interrupt-controller@fee00000 {
+ compatible = "intel,ce4100-lapic";
+ reg = <0xfee00000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic
2022-11-24 8:41 [PATCH v5 0/4] x86/of: Add support for interrupt mode config for x86 OF systems Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Rahul Tanwar
@ 2022-11-24 8:41 ` Rahul Tanwar
2022-11-30 21:21 ` Rob Herring
2022-12-02 14:03 ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Rahul Tanwar
3 siblings, 2 replies; 11+ messages in thread
From: Rahul Tanwar @ 2022-11-24 8:41 UTC (permalink / raw)
To: Rahul Tanwar, Andy Shevchenko, linux-kernel, devicetree
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
linux-lgm-soc
Intel defines a few possible interrupt delivery modes. With respect
to boot/init time, mainly two interrupt delivery modes are possible.
PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
For ACPI or MPS spec compliant systems, it is figured out by some read
only bit field/s available in their respective defined data structures.
But for OF based systems, it is by default set to PIC mode. Presently,
it is hardcoded to legacy PIC mode for OF based x86 systems with no
option to choose the configuration between PIC mode & virtual wire mode.
For this purpose, introduce a new boolean property for interrupt
controller node of lapic which can allow it to be configured to virtual
wire mode as well.
Property name: 'intel,virtual-wire-mode'
Type: Boolean
If not present/not defined, interrupt delivery mode defaults to legacy PIC
mode. If present/defined, interrupt delivery mode is set to virtual wire
mode.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
.../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
index 55184cb49432..d2d0145cb889 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -39,6 +39,19 @@ properties:
'#interrupt-cells':
const: 2
+ intel,virtual-wire-mode:
+ description: Intel defines a few possible interrupt delivery
+ modes. With respect to boot/init time, mainly two interrupt
+ delivery modes are possible.
+ PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
+ Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
+ For ACPI or MPS spec compliant systems, it is figured out by some read
+ only bit field/s available in their respective defined data structures.
+ For OF based systems, it is by default set to PIC mode.
+ But if this optional boolean property is set, then the interrupt delivery
+ mode is configured to virtual wire compatibility mode.
+ type: boolean
+
required:
- compatible
- reg
@@ -54,4 +67,5 @@ examples:
reg = <0xfee00000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
+ intel,virtual-wire-mode;
};
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic
2022-11-24 8:41 ` [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Rahul Tanwar
@ 2022-11-30 21:21 ` Rob Herring
2022-12-02 14:03 ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
1 sibling, 0 replies; 11+ messages in thread
From: Rob Herring @ 2022-11-30 21:21 UTC (permalink / raw)
To: Rahul Tanwar
Cc: devicetree, Krzysztof Kozlowski, x86, Borislav Petkov,
Andy Shevchenko, Marc Zyngier, linux-kernel, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, linux-lgm-soc,
Rob Herring
On Thu, 24 Nov 2022 16:41:41 +0800, Rahul Tanwar wrote:
> Intel defines a few possible interrupt delivery modes. With respect
> to boot/init time, mainly two interrupt delivery modes are possible.
> PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
> Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
>
> For ACPI or MPS spec compliant systems, it is figured out by some read
> only bit field/s available in their respective defined data structures.
> But for OF based systems, it is by default set to PIC mode. Presently,
> it is hardcoded to legacy PIC mode for OF based x86 systems with no
> option to choose the configuration between PIC mode & virtual wire mode.
>
> For this purpose, introduce a new boolean property for interrupt
> controller node of lapic which can allow it to be configured to virtual
> wire mode as well.
>
> Property name: 'intel,virtual-wire-mode'
> Type: Boolean
>
> If not present/not defined, interrupt delivery mode defaults to legacy PIC
> mode. If present/defined, interrupt delivery mode is set to virtual wire
> mode.
>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
> ---
> .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [tip: x86/apic] dt-bindings: x86: apic: Introduce new optional bool property for lapic
2022-11-24 8:41 ` [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Rahul Tanwar
2022-11-30 21:21 ` Rob Herring
@ 2022-12-02 14:03 ` tip-bot2 for Rahul Tanwar
1 sibling, 0 replies; 11+ messages in thread
From: tip-bot2 for Rahul Tanwar @ 2022-12-02 14:03 UTC (permalink / raw)
To: linux-tip-commits
Cc: Andy Shevchenko, Rahul Tanwar, Thomas Gleixner, Rob Herring, x86,
linux-kernel
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: b3a9801cccefda304263b4e84e9dfe49057f3c29
Gitweb: https://git.kernel.org/tip/b3a9801cccefda304263b4e84e9dfe49057f3c29
Author: Rahul Tanwar <rtanwar@maxlinear.com>
AuthorDate: Thu, 24 Nov 2022 16:41:41 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 02 Dec 2022 14:57:14 +01:00
dt-bindings: x86: apic: Introduce new optional bool property for lapic
X86 defines a few possible interrupt delivery modes. With respect to
boot/init time, mainly two interrupt delivery modes are possible.
- PIC Mode: Legacy external 8259 compliant PIC interrupt controller
- Virtual Wire Mode: Use lapic as virtual wire interrupt delivery mode
ACPI and MPS spec compliant systems provide this information, but for OF
based systems, it is by default set to PIC mode.
In fact it is hardcoded to legacy PIC mode for OF based x86 systems with no
option to choose the configuration between PIC mode & virtual wire mode.
For this purpose, introduce a new boolean property for the lapic interrupt
controller node which allows to configure it for virtual wire mode as well.
Property name: 'intel,virtual-wire-mode'
Type: Boolean
If not present/not defined, interrupt delivery mode defaults to legacy PIC
mode. If present/defined, interrupt delivery mode is set to virtual wire
mode.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221124084143.21841-3-rtanwar@maxlinear.com
---
Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
index 55184cb..d2d0145 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -39,6 +39,19 @@ properties:
'#interrupt-cells':
const: 2
+ intel,virtual-wire-mode:
+ description: Intel defines a few possible interrupt delivery
+ modes. With respect to boot/init time, mainly two interrupt
+ delivery modes are possible.
+ PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
+ Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
+ For ACPI or MPS spec compliant systems, it is figured out by some read
+ only bit field/s available in their respective defined data structures.
+ For OF based systems, it is by default set to PIC mode.
+ But if this optional boolean property is set, then the interrupt delivery
+ mode is configured to virtual wire compatibility mode.
+ type: boolean
+
required:
- compatible
- reg
@@ -54,4 +67,5 @@ examples:
reg = <0xfee00000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
+ intel,virtual-wire-mode;
};
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl()
2022-11-24 8:41 [PATCH v5 0/4] x86/of: Add support for interrupt mode config for x86 OF systems Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Rahul Tanwar
@ 2022-11-24 8:41 ` Rahul Tanwar
2022-12-02 14:03 ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24 8:41 ` [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Rahul Tanwar
3 siblings, 1 reply; 11+ messages in thread
From: Rahul Tanwar @ 2022-11-24 8:41 UTC (permalink / raw)
To: Rahul Tanwar, Andy Shevchenko, linux-kernel, devicetree
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
linux-lgm-soc
Use latest available pr_lvl() instead of older printk(KERN_LVL)
Just a upgrade of print utilities usage no functional changes.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
arch/x86/kernel/devicetree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 5cd51f25f446..fcc6f1b7818f 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *dn)
ret = of_address_to_resource(dn, 0, &r);
if (ret) {
- printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
+ pr_err("Can't obtain address from device node %pOF.\n", dn);
return;
}
mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
@@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void)
of_ioapic = 1;
return;
}
- printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
+ pr_err("Error: No information about IO-APIC in OF.\n");
}
#else
static void __init dtb_ioapic_setup(void) {}
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [tip: x86/apic] x86/of: Replace printk(KERN_LVL) with pr_lvl()
2022-11-24 8:41 ` [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Rahul Tanwar
@ 2022-12-02 14:03 ` tip-bot2 for Rahul Tanwar
0 siblings, 0 replies; 11+ messages in thread
From: tip-bot2 for Rahul Tanwar @ 2022-12-02 14:03 UTC (permalink / raw)
To: linux-tip-commits
Cc: Andy Shevchenko, Rahul Tanwar, Thomas Gleixner, x86, linux-kernel
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 535403323b4dcdc363e7ea265df62481b903826b
Gitweb: https://git.kernel.org/tip/535403323b4dcdc363e7ea265df62481b903826b
Author: Rahul Tanwar <rtanwar@maxlinear.com>
AuthorDate: Thu, 24 Nov 2022 16:41:42 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 02 Dec 2022 14:57:14 +01:00
x86/of: Replace printk(KERN_LVL) with pr_lvl()
Use pr_lvl() instead of the deprecated printk(KERN_LVL).
Just a upgrade of print utilities usage. no functional changes.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221124084143.21841-4-rtanwar@maxlinear.com
---
arch/x86/kernel/devicetree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 59438d2..484783f 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -243,7 +243,7 @@ static void __init dtb_add_ioapic(struct device_node *dn)
ret = of_address_to_resource(dn, 0, &r);
if (ret) {
- printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
+ pr_err("Can't obtain address from device node %pOF.\n", dn);
return;
}
mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
@@ -260,7 +260,7 @@ static void __init dtb_ioapic_setup(void)
of_ioapic = 1;
return;
}
- printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
+ pr_err("Error: No information about IO-APIC in OF.\n");
}
#else
static void __init dtb_ioapic_setup(void) {}
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration
2022-11-24 8:41 [PATCH v5 0/4] x86/of: Add support for interrupt mode config for x86 OF systems Rahul Tanwar
` (2 preceding siblings ...)
2022-11-24 8:41 ` [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Rahul Tanwar
@ 2022-11-24 8:41 ` Rahul Tanwar
2022-12-02 14:03 ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
3 siblings, 1 reply; 11+ messages in thread
From: Rahul Tanwar @ 2022-11-24 8:41 UTC (permalink / raw)
To: Rahul Tanwar, Andy Shevchenko, linux-kernel, devicetree
Cc: Thomas Gleixner, Marc Zyngier, Rob Herring, Krzysztof Kozlowski,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
linux-lgm-soc
Presently, init/boot time interrupt delivery mode is enumerated
only for ACPI enabled systems by parsing MADT table or for older
systems by parsing MP table. But for OF based x86 systems, it is
assumed & hardcoded to legacy PIC mode. This causes boot time crash
for platforms which do not use 8259 compliant legacy PIC.
Add support for configuration of init time interrupt delivery mode
for x86 OF based systems by introducing a new optional boolean
property 'intel,virtual-wire-mode' for interrupt-controller node
of local APIC. This property emulates IMCRP Bit 7 of MP feature
info byte 2 of MP floating pointer structure.
Defaults to legacy PIC mode if absent. Configures it to virtual
wire compatibility mode if present.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
arch/x86/kernel/devicetree.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index fcc6f1b7818f..458e43490414 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void)
return;
}
smp_found_config = 1;
- pic_mode = 1;
+ if (of_property_read_bool(dn, "intel,virtual-wire-mode")) {
+ pr_info("Virtual Wire compatibility mode.\n");
+ pic_mode = 0;
+ } else {
+ pr_info("IMCR and PIC compatibility mode.\n");
+ pic_mode = 1;
+ }
+
register_lapic_address(lapic_addr);
}
--
2.17.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [tip: x86/apic] x86/of: Add support for boot time interrupt delivery mode configuration
2022-11-24 8:41 ` [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Rahul Tanwar
@ 2022-12-02 14:03 ` tip-bot2 for Rahul Tanwar
0 siblings, 0 replies; 11+ messages in thread
From: tip-bot2 for Rahul Tanwar @ 2022-12-02 14:03 UTC (permalink / raw)
To: linux-tip-commits
Cc: Rahul Tanwar, Thomas Gleixner, Andy Shevchenko, x86, linux-kernel
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 2833275568755eb937a52c358bf8bfa7125a463e
Gitweb: https://git.kernel.org/tip/2833275568755eb937a52c358bf8bfa7125a463e
Author: Rahul Tanwar <rtanwar@maxlinear.com>
AuthorDate: Thu, 24 Nov 2022 16:41:43 +08:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 02 Dec 2022 14:57:14 +01:00
x86/of: Add support for boot time interrupt delivery mode configuration
Presently, init/boot time interrupt delivery mode is enumerated only for
ACPI enabled systems by parsing MADT table or for older systems by parsing
MP table. But for OF based x86 systems, it is assumed & hardcoded to be
legacy PIC mode. This causes a boot time crash for platforms which do not
provide a 8259 compliant legacy PIC.
Add support for configuration of init time interrupt delivery mode for x86
OF based systems by introducing a new optional boolean property
'intel,virtual-wire-mode' for the local APIC interrupt-controller
node. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP
floating pointer structure.
Defaults to legacy PIC mode if absent. Configures it to virtual wire
compatibility mode if present.
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221124084143.21841-5-rtanwar@maxlinear.com
---
arch/x86/kernel/devicetree.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 484783f..28da5dd 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -162,7 +162,14 @@ static void __init dtb_lapic_setup(void)
return;
}
smp_found_config = 1;
- pic_mode = 1;
+ if (of_property_read_bool(dn, "intel,virtual-wire-mode")) {
+ pr_info("Virtual Wire compatibility mode.\n");
+ pic_mode = 0;
+ } else {
+ pr_info("IMCR and PIC compatibility mode.\n");
+ pic_mode = 1;
+ }
+
register_lapic_address(lapic_addr);
}
^ permalink raw reply [flat|nested] 11+ messages in thread